HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 25

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

11.2 Register Descriptions......................................................................................................... 333
11.3 Operation........................................................................................................................... 345
11.4 Compare Match Timer (CMT) .......................................................................................... 376
11.5 Examples of Use................................................................................................................ 383
11.6 Usage Notes....................................................................................................................... 387
Section 12 Timer (TMU)
12.1 Overview ........................................................................................................................... 389
12.2 TMU Registers .................................................................................................................. 392
11.1.1 Features ................................................................................................................ 327
11.1.2 Block Diagram ..................................................................................................... 329
11.1.3 Pin Configuration ................................................................................................. 330
11.1.4 Register Configuration ......................................................................................... 331
11.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)........................................... 333
11.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) .................................. 334
11.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) ......................... 335
11.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) ................................... 336
11.2.5 DMA Operation Register (DMAOR) ................................................................... 343
11.3.1 DMA Transfer Flow............................................................................................. 345
11.3.2 DMA Transfer Requests....................................................................................... 347
11.3.3 Channel Priority ................................................................................................... 349
11.3.4 DMA Transfer Types ........................................................................................... 352
11.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ........................... 363
11.3.6 Source Address Reload Function ......................................................................... 372
11.3.7 DMA Transfer Ending Conditions ....................................................................... 374
11.4.1 Overview .............................................................................................................. 376
11.4.2 Register Descriptions ........................................................................................... 377
11.4.3 Operation.............................................................................................................. 380
11.4.4 Compare Match .................................................................................................... 381
11.5.1 Example of DMA Transfer between On-Chip IrDA and External Memory ........ 383
11.5.2 Example of DMA Transfer between A/D Converter and External Memory ........ 384
11.5.3 Example of DMA Transfer between External Memory and SCIF Transmitter
12.1.1 Features ................................................................................................................ 389
12.1.2 Block Diagram ..................................................................................................... 390
12.1.3 Pin Configuration ................................................................................................. 391
12.1.4 Register Configuration ......................................................................................... 391
12.2.1 Timer Output Control Register (TOCR) .............................................................. 392
12.2.2 Timer Start Register (TSTR)................................................................................ 392
12.2.3 Timer Control Registers (TCR)............................................................................ 393
12.2.4 Timer Constant Registers (TCOR) ....................................................................... 397
12.2.5 Timer Counters (TCNT)....................................................................................... 397
12.2.6 Input Capture Register (TCPR2) .......................................................................... 399
(Indirect Address On)........................................................................................... 385
................................................................................................... 389
Rev. 5.00, 09/03, page xxiii of xliv