HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 573

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bits 15 to 12—Number of Parity Errors 3 to 0 (PER3 to PER0): Indicate the quantity of data
including a parity error in the receive data stored in the receive FIFO data register (SCFRDR).
The value indicated by bits 15 to 12 represents the number of parity errors in SCFRDR.
Bits 11 to 8—Number of Framing Errors 3 to 0 (FER3 to FER0): Indicate the quantity of data
including a framing error in the receive data stored in SCFRDR. The value indicated by bits 11 to
8 represents the number of framing errors in SCFRDR.
16.2.8
The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a reset and in
module standby or standby mode. Each channel has independent baud rate generator control, so
different values can be set in two channels.
The SCBRR setting is calculated as follows:
Asynchronous mode:
Upper 8 bits:
Initial value:
Initial value:
B:
N:
P : Operating frequency for peripheral modules (MHz)
n:
N =
Bit Rate Register (SCBRR)
R/W:
R/W:
Bit rate (bits/s)
SCBRR setting for baud rate generator (0
Baud rate generator clock source (n
n, see table 16.3.)
64
Bit:
2
P
2n – 1
PER3
R/W
15
R
0
7
1
B
PER2
10
R/W
14
R
0
6
1
6
– 1
PER1
R/W
13
R
0
5
1
PER0
0, 1, 2, 3) (for the clock sources and values of
R/W
12
R
0
4
1
N
FER3
255)
R/W
11
R
0
3
1
Rev. 5.00, 09/03, page 527 of 760
FER2
R/W
10
R
0
2
1
FER1
R/W
R
9
0
1
1
FER0
R/W
R
8
0
0
1