HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 383

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bits 31 to 21—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 20—Direct/Indirect Selection (DI): Selects direct address mode or indirect address mode in
channel 3.
This bit is only valid in CHCR3. Writing to this bit is invalid in CHCR0 to CHCR2; 0 is read if
this bit is read. The write value should always be 0. When using 16-byte transfer, direct address
mode must be specified. Operation is not guaranteed if indirect address mode is specified.
Bit 19—Source Address Reload Bit (RO): Selects whether the source address initial value is
reloaded in channel 2.
This bit is only valid in CHCR2. Writing to this bit is invalid in CHCR0, CHCR1, and CHCR3; 0
is read if this bit is read. The write value should always be 0. When using 16-byte transfer, this bit
must be cleared to 0, specifying non-reloading. Operation is not guaranteed if reloading is
specified.
Bit 18—Request Check Level Bit (RL): Specifies whether DRAK (DREQ acknowledge) signal
output is active-high or active-low.
This bit is only valid in CHCR0 and CHCR1. Writing to this bit is invalid in CHCR2 and
CHCR3; 0 is read if this bit is read. The write value should always be 0.
Bit 20: DI
0
1
Bit 19: RO
0
1
Bit 18: RL
0
1
Description
Direct address mode operation for channel 3
Indirect address mode operation for channel 3
Description
Source address is not reloaded
Source address is reloaded
Description
Active-low DRAK output
Active-high DRAK output
Rev. 5.00, 09/03, page 337 of 760
(Initial value)
(Initial value)
(Initial value)