HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 286

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 2n + 1: AnSZ1
0
1
0
1
10.2.3
Wait state control register 1 (WCR1) is a 16-bit readable/writable register that specifies the
number of idle (wait) state cycles inserted for each area. For some memories, data bus drive may
not be turned off quickly even when the read signal from the external device is turned off. This
can result in conflicts between data buses when consecutive memory accesses are to different
memories or when a write immediately follows a memory read. This LSI automatically inserts the
number of idle states set in WCR1 in those cases.
WCR1 is initialized to H'3FF3 by a power-on reset. It is not initialized by a manual reset or in
standby mode, and retains its contents.
Rev. 5.00, 09/03, page 240 of 760
Initial value:
Initial value:
Wait State Control Register 1 (WCR1)
R/W:
R/W:
Bit:
Bit:
WAITSE
Bit 2n: AnSZ0
0
1
0
1
0
1
0
1
A3IW1
R/W
R/W
15
L
0
7
1
A3IW0
R/W
14
—
R
0
6
1
A6IW1
A2IW1
R/W
R/W
Port A / B
Not used
Used
13
1
5
1
A6IW0
A2IW0
R/W
R/W
12
1
4
1
A5IW1
R/W
11
—
Description
Reserved (Setting prohibited)
Byte (8-bit) size
Word (16-bit) size
Longword (32-bit) size
Reserved (Setting prohibited)
Byte (8-bit) size
Word (16-bit) size
Reserved (Setting prohibited)
R
1
3
0
A5IW0
R/W
10
—
R
1
2
0
A4IW1
A0IW1
R/W
R/W
9
1
1
1
A4IW0
A0IW0
R/W
R/W
8
1
0
1