HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 261

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

9.7
9.7.1
The watchdog timer counter (WTCNT) is an 8-bit readable/writable counter that increments on the
selected clock. WTCNT differs from other registers in that it is more difficult to write to. See
section 9.7.3, Notes on Register Access, for details. When an overflow occurs, it generates a reset
in watchdog timer mode and an interrupt in interval time mode. Its address is H'FFFFFF84. The
WTCNT counter is initialized to H'00 only by a power-on reset through the RESETP pin. Use
word access to write to the WTCNT counter, with H'5A in the upper byte. Use byte access to read
WTCNT.
9.7.2
The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register
composed of bits to select the clock used for the count, bits to select the timer mode, and overflow
flags. WTCSR differs from other registers in that it is more difficult to write to. See section 9.7.3,
Notes on Register Access, for details. Its address is H'FFFFFF86. The WTCSR register is
initialized to H'00 only by a power-on reset through the RESETP pin. When a WDT overflow
causes an internal reset, WTCSR retains its value. When used to count the clock settling time for
canceling a standby, it retains its value after counter overflow. Use word access to write to the
WTCSR counter, with H'A5 in the upper byte. Use byte access to read WTCSR.
Bit 7—Timer Enable (TME): Starts and stops timer operation. Clear this bit to 0 when using the
WDT in standby mode or when changing the clock frequency.
Bit 7: TME
0
1
Initial value:
Initial value:
WDT Registers
Watchdog Timer Counter (WTCNT)
Watchdog Timer Control/Status Register (WTCSR)
R/W:
R/W:
Bit:
Bit:
TME
R/W
R/W
7
0
7
0
Description
Timer disabled: Count-up stops and WTCNT value is retained
Timer enabled
WT/IT
R/W
R/W
6
0
6
0
RSTS
R/W
R/W
5
0
5
0
WOVF
R/W
R/W
4
0
4
0
IOVF
R/W
R/W
3
0
3
0
Rev. 5.00, 09/03, page 215 of 760
CKS2
R/W
R/W
2
0
2
0
CKS1
R/W
R/W
1
0
1
0
(Initial value)
CKS0
R/W
R/W
0
0
0
0