HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 195

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

7.1
The user break controller (UBC) provides functions that simplify program debugging. This
function makes it easy to design an effective self-monitoring debugger, enabling the chip to debug
programs without using an in-circuit emulator. Break conditions that can be set in the UBC are
instruction fetch or data read/write, data size, data content, address value, and stop timing during
instruction fetches.
7.1.1
The user break controller has the following features:
The following break comparison conditions can be set.
Number of break channels: two channels (channels A and B)
User break can be requested as either the independent or sequential condition on channels A
and B (sequential break setting: channel A and, then channel B match with logical AND, but
not in the same bus cycle).
User break is generated upon satisfying break conditions. A user-designed user-break
condition exception processing routine can be run.
In an instruction fetch cycle, it can be selected that a break is set before or after an instruction
is executed.
Maximum repeat times for the break condition: 2
Eight pairs of branch source/destination buffers.
Address (Compares 40 bits comprised of a 32-bit logical address prefixed with an ASID
address. Comparison bits are maskable in 32-bit units, user can easily program it to mask
addresses at bottom 12 bits (4-k page), bottom 10 bits (1-k page), or any size of page, etc.
One of two address buses (CPU address bus (LAB), cache address bus (IAB)) can be
selected.
Data (only on channel B, 32-bit maskable)
One of the two data buses (CPU data bus (LDB), cache data bus (IDB)) can be selected.
Bus master: CPU cycle or DMAC cycle
Bus cycle: instruction fetch or data access
Read/write
Operand size: byte, word, or longword
Overview
Features
Section 7 User Break Controller
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Rev. 5.00, 09/03, page 149 of 760