HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 209

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 21—Break ASID Mask A (BASMA): Specifies whether the bits of the channel A break
ASID7-ASID0 (BASA7 to BASA0) set in BASRA are masked or not.
Bit 20—Break ASID Mask B (BASMB): Specifies whether the bits of channel B break ASID7-
ASID0 (BASB7 to BASB0) set in BASRB are masked or not.
Bits 19 to 16—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 15—CPU Condition Match Flag A (SCMFCA): When the CPU bus cycle condition in the
break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to
clear this flag, write 0 into this bit.
Bit 14—CPU Condition Match Flag B (SCMFCB): When the CPU bus cycle condition in the
break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to
clear this flag, write 0 into this bit.
Bit 21: BASMA Description
0
1
Bit 20: BASMB Description
0
1
Bit 15:
SCMFCA
0
1
Bit 14:
SCMFCB
0
1
All BASRA bits are included in break condition, ASID is checked
No BASRA bits are included in break condition, ASID is not checked
All BASRB bits are included in break condition, ASID is checked
No BASRB bits are included in break condition, ASID is not checked
Description
The CPU cycle condition for channel A does not match
The CPU cycle condition for channel A matches
Description
The CPU cycle condition for channel B does not match
The CPU cycle condition for channel B matches
Rev. 5.00, 09/03, page 163 of 760
(Initial value)
(Initial value)
(Initial value)
(Initial value)