HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 654

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

19.12.2 Port L Data Register (PLDR)
The port L data register (PLDR) is an 8-bit read-only register that stores data for pins PTL7 to
PTL0. Bits PL7DT to PL0DT correspond to pins PTL7 to PTL0. When the function is general
input port, if the port is read, the corresponding pin level is read. Table 19.22 shows the function
of PLDR.
PKDR is initialized to H'00 by power-on reset. It retains its previous value in software standby
mode and sleep mode, and in a manual reset.
The port L is also used as an analog pin, therefore does not have a pull-up MOS.
Table 19.22 Port L Data Register (PLDR) Read/Write Operation
PLnMD1
0
1
Rev. 5.00, 09/03, page 608 of 760
Initial value:
PLnMD0
0
1
0
1
R/W:
Bit:
PL7DT
R
7
0
Pin State
Other function
(see table 18.1)
Reserved
Input
Input
PL6DT
R
6
0
PL5DT
Read
H'00
H'00
Pin state
Pin state
R
5
0
PL4DT
R
4
0
Write
Ignored (no effect on pin state)
Ignored (no effect on pin state)
Ignored (no effect on pin state)
Ignored (no effect on pin state)
PL3DT
R
3
0
PL2DT
R
2
0
PL1DT
R
1
0
(n = 0 to 7)
PL0DT
R
0
0