HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 506

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in SCSSR. When TDRE is cleared to 0, the SCI recognizes
2. After loading the data from SCTDR into SCTSR, the SCI sets the TDRE bit to 1 and starts
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new
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that the transmit data register (SCTDR) contains new data, and loads this data from SCTDR
into the transmit shift register (SCTSR).
transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in SCSCR, the SCI
requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted
in the following order from the TxD pin:
a. Start bit: One 0 bit is output.
b. Transmit data: Seven or eight bits of data are output, LSB first.
c. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor
d. Stop bit: One or two 1-bits (stop bits) are output.
e. Marking: Output of 1-bits continues until the start bit of the next transmit data.
data from SCTDR into SCTSR, outputs the stop bit, then begins serial transmission of the next
frame. If TDRE is 1, the SCI sets the TEND bit to 1 in SCSSR, outputs the stop bit, then
continues output of 1-bits (marking). If the transmit-end interrupt enable bit (TEIE) in SCSCR
is set to 1, a transmit-end interrupt (TEI) is requested.
bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can
also be selected.