DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 109

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DS33Z41

Manufacturer Part Number
DS33Z41
Description
Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS33Z41

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Bit 0: Receive PMU Update (RPMUU). This signal causes the receive cell/packet processor block performance
monitoring registers to be updated. A 0 to 1 transition causes the performance monitoring registers to be updated
with the latest data, and resets the associated counters. This bit updates performance monitoring counters for the
Serial Interface.
Bit 0: Receive PMU Update Status (RPMUUS). This bit is set when the Transmit PMU Update is completed.
This bit is cleared when RPMUU is set to 0.
Bit 3: SAPI High is Not Equal to
SAPIH is not equal to LI.TRX86SAPIH. This latched status bit is cleared upon read.
Bit 2: SAPI Low is Not Equal to
SAPIL is not equal to LI.TRX86SAPIL. This latched status bit is cleared upon read.
Bit 1: Control is Not Equal to
LI.TRX8C. This latched status bit is cleared upon read.
Bit 0: Address is Not Equal to
equal to LI.TRX86A. This latched status bit is cleared upon read.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
7
0
7
0
LI.RHPMUU
Serial Interface Receive HDLC PMU Update Register
120h
LI.RHPMUS
Serial Interface Receive HDLC PMU Update Status Register
121h
6
6
0
6
0
LI.TRX8C
LI.TRX86A
LI.RX86S
Receive X.86 Latched Status Register
122h
LI.TRX86SAPIL
LI.TRX86SAPIH
5
(CNE). This latched status bit is set if the control field is not equal to
5
0
5
0
(ANE). This latched status bit is set if the X.86 Address field is not
Latched Status (SAPILNE). This latched status bit is set if
Latched Status (SAPIHNE). This latched status bit is set if
109 of 167
4
0
4
0
4
SAPIHNE
3
3
0
3
0
SAPILNE
2
2
0
2
0
CNE
1
1
0
1
0
RPMUUS
RPMUU
ANE
0
0
0
0
0

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