DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 16

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

COL_DET
NAME
MDIO
MDC
CS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
D0
D1
D2
D3
D4
D5
D6
D7
C12
C13
PIN
B13
A1
B1
A2
B2
C2
A3
B3
C3
A4
B4
A5
A6
A7
B5
B6
B7
C5
C6
C1
TYPE
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IO
O
I
I
I
I
I
I
I
I
I
I
I
I
Collision Detect (MII). Asserted by the MAC PHY to indicate that a
collision is occurring. In DCE Mode this signal should be connected to
ground. This signal is only valid in half duplex mode, and is ignored in
full duplex mode
Management Data Clock (MII). Clocks management data between the
PHY and DS33Z41. The clock is derived from SYSCLKI, with a
maximum frequency is 1.67MHz. The user must leave this pin
unconnected in the DCE Mode.
MII Management data IO (MII). Data path for control information
between the PHY and DS33Z41. When not used, pull to logic high
externally through a 10kΩ resistor. The MDC and MDIO pins are used
to write or read up to 32 Control and Status Registers in 32 PHY
Controllers. This port can also be used to initiate Auto-Negotiation for
the PHY. The user must leave this pin unconnected in the DCE Mode.
Address Bit 0. Address bit 0 of the microprocessor interface. Least
Significant Bit.
Address Bit 1. Address bit 1 of the microprocessor interface.
Address Bit 2. Address bit 2 of the microprocessor interface.
Address Bit 3. Address bit 3 of the microprocessor interface.
Address Bit 4. Address bit 4 of the microprocessor interface.
Address Bit 5. Address bit 5 of the microprocessor interface.
Address Bit 6. Address bit 6 of the microprocessor interface.
Address Bit 7. Address bit 7 of the microprocessor interface.
Address Bit 8. Address bit 8 of the microprocessor interface.
Address Bit 9. Address bit 9 of the microprocessor interface. Most
Significant Bit.
Data Bit 0. Bidirectional data bit 0 of the microprocessor interface.
Least Significant Bit. Not driven when CS = 1 or RST = 0.
Data Bit 1. Bidirectional data bit 1 of the microprocessor interface. Not
driven when CS = 1 or RST = 0.
Data Bit 2. Bidirectional data bit 2 of the microprocessor interface. Not
driven when CS = 1 or RST = 0.
Data Bit 3. Bidirectional data bit 3 of the microprocessor interface. Not
driven when CS = 1 or RST = 0.
Data Bit 4. Bidirectional data bit 4 of the microprocessor interface. Not
driven when CS = 1 or RST = 0.
Data Bit 5. Bidirectional data bit 5 of the microprocessor interface. Not
driven when CS = 1 or RST = 0.
Data Bit 6. Bidirectional data bit 6 of the microprocessor interface. Not
driven when CS = 1 or RST = 0.
Data Bit 7. Bidirectional data bit 7 of the microprocessor interface. Most
Significant Bit. Not driven when CS = 1 or RST = 0.
Chip Select. This pin must be taken low for read/write operations.
When CS is high, the RD/DS and WR signals are ignored.
MICROPROCESSOR PORT
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FUNCTION