DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 49
DS33Z41
Manufacturer Part Number
DS33Z41
Description
Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33Z41.pdf
(167 pages)
Specifications of DS33Z41
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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DS33Z41 Quad IMUX Ethernet Mapper
8.15.2 Receive Data Interface
8.15.2.1 Receive Pattern Detection
The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the
incoming pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant
bit (LSB) or bit 1 to the most significant bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern
n
y
(generating polynomial x
+ x
+ 1), the feedback is an XOR of bit n and bit y. For a repetitive pattern (length n),
the feedback is bit n. The values for n and y are individually programmable (1 to 32). The output of the receive
pattern generator is the feedback. If QRSS is enabled, the feedback is an XOR of bits 17 and 20, and the output
is forced to one if the next 14 bits are all zeros. QRSS is programmable (on or off). For PRBS and QRSS
patterns, the feedback is forced to one if bits 1 through 31 are all zeros. Depending on the type of pattern
programmed, pattern detection performs either PRBS synchronization or repetitive pattern synchronization.
8.15.2.2 PRBS Synchronization
PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The
receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and
then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the incoming pattern.
If at least is incoming bits in the current 64-bit window do not match the receive pattern generator, automatic
pattern resynchronization is initiated. Automatic pattern resynchronization can be disabled.
Figure 8-12. PRBS Synchronization State Diagram
Sync
1 bit error
Verify
Load
32 bits loaded
8.15.3 Repetitive Pattern Synchronization
Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern.
The receive pattern generator is synchronized by searching each incoming data stream bit position for the
repetitive pattern, and then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match
the incoming pattern. If at least sis incoming bits in the current 64-bit window do not match the receive PRBS
pattern generator, automatic pattern resynchronization is initiated. Automatic pattern resynchronization can be
disabled.
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