DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 19

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SDMASK[0]
SDMASK[1]
SDMASK[2]
SDMASK[3]
SYSCLKI
SDCLKO
JTCLK
NAME
QOVF
JTRST
SCAS
SDCS
JTDO
JTMS
SWE
JTDI
M10
G13
PIN
M4
G4
M9
H4
N6
N5
C7
E6
D4
E5
E4
L6
F7
(4mA)
TYPE
Ipu
Ipu
Ipu
Ipu
Oz
O
O
O
O
O
O
I
SDRAM Column Address Strobe. Active-low output, used to latch the
column address on the rising edge of SDCLKO. It is used with
commands for Bank Activate, Precharge, and Mode Register Write.
SDRAM Write Enable. This active-low output enables write operation
and auto precharge.
SDRAM Mask 0 to 3. When high, a write is done for that byte. The
least significant byte is SDATA7 to SDATA0. The most significant byte
is SDATA31 to SDATA24.
SDRAM CLK Out. System clock output to the SDRAM. This clock is a
buffered version of SYSCLKI.
System Clock In. 100MHz System Clock input to the DS33Z41, used
for internal operation. This clock is buffered and provided at SDCLKO
for the SDRAM interface. The DS33Z41 also provides a divided version
output at the REF_CLKO pin. A clock supply with ±100ppm frequency
accuracy is suggested.
SDRAM Chip Select. Active-low output enables SDRAM access.
Queue Overflow. This pin goes high when the transmit or receive
queue has overflowed. This pin will go low when the high watermark is
reached again.
JTAG Reset. JTRST is used to asynchronously reset the test access
port controller. After power-up, a rising edge on JTRST will reset the
test port and cause the device I/O to enter the JTAG DEVICE ID mode.
Pulling JTRST low restores normal device operation. JTRST is pulled
HIGH internally via a 10kΩ resistor operation. If boundary scan is not
used, this pin should be held low.
JTAG Clock. This signal is used to shift data into JTDI on the rising
edge and out of JTDO on the falling edge.
JTAG Data Out. Test instructions and data are clocked out of this pin
on the falling edge of JTCLK. If not used, this pin should be left
unconnected.
JTAG Data In. Test instructions and data are clocked into this pin on
the rising edge of JTCLK. This pin has a 10kΩ pullup resistor.
JTAG Mode Select. This pin is sampled on the rising edge of JTCLK
and is used to place the test access port into the various defined IEEE
1149.1 states. This pin has a 10kΩ pullup resistor.
JTAG INTERFACE
QUEUE STATUS
19 of 167
FUNCTION