DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 56

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-15. X.86 Encapsulation of the MAC field
The DS33Z41 will encode the MAC Frame with the LAPS encapsulation on a complete serial stream if configured
for X.86 mode in the register LI.TX86E. The DS33Z41 provides the following functions:
The sequence of processing performed by the receiver is as follows:
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Control Registers for Address, SAPI, Destination Address, Source Address.
32 bit FCS enabled.
Programmable X
Programmable octets X
Detect the Start Flag (7E).
Remove Rate adaptation octets 7d, dd.
Perform transparency-processing 7d, 5e is converted to 7e and 7d, 5d is converted to 7d.
Check for a valid Address, Control and SAPI fields
Perform FCS checking.
Detect the closing flag.
MSB
2nd Octect of SAPI(0x01)
1st Octect of SAPI(0xfe)
Destination Adrs(DA)
Source Adrs(SA)
MAC Client Data
43
Address(0x04)
FCS for LAPS
Control(0x03)
FCS for MAC
+1 scrambling.
Length/Type
Flag(0x7E)
Flag(0x7E)
PAD
43
+1 descrambling.
Number of Bytes
LSB
46-1500
56 of 167
2
4
4
1
1
1
1
1
6
6
(LI.TRX86A
to LI.TRX86SAPIL).