DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 13
DS33Z41
Manufacturer Part Number
DS33Z41
Description
Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33Z41.pdf
(167 pages)
Specifications of DS33Z41
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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DS33Z41 Quad IMUX Ethernet Mapper
5 MAJOR OPERATING MODES
Operation of the DS33Z41 operation requires a host microprocessor for initialization and maintenance of the link
aggregation functions. Microprocessor control is possible through the 8-bit parallel control port. More information
on microprocessor control is available in Section 8.1.
6 BLOCK DIAGRAMS
Figure 6-1. Detailed Block Diagram
50 or 25 Mhz Oscillator
Buffer
REF_CLK
Microport
Div by 1,2,4,8,10
Output clocks:
50,25 Mhz,2.5 Mhz
TSER
TX_CLK1
HDLC
TCLKI1
+
RXD
MAC
Serial
Line 1
CIR
IMUX
RMII
Interface
RX_CLK1
Arbiter
RCLKI1
MII
TXD
RSER
X.86
MDC
100 Mhz Oscillator
JTAG
Buffer Dev
Div by 2,4,12
SYSCLKI
SDRAM
Output Clocks
Interface
25,50
Mhz
SDCLKO
REF_CLKO
50 or 25 Mhz
SDRAM
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