DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 48

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.14.3 PHY MII Management Block and MDIO Interface
The MII Management Block allows for the host to control up to 32 PHYs, each with 32 registers. The MII block
communicates with the external PHY using 2-wire serial interface composed of MDC (serial clock) and MDIO for
data. The MDIO data is valid on the rising edge of the MDC clock. The Frame format for the MII Management
Interface is shown
indirect SU.MACMIIA MII Management Address Register and data is passed through the indirect SU.MACMIID
Data Register. These indirect registers are accessed through the MAC Control Registers defined in
The MDC clock is internally generated and runs at 1.67MHz. Note that the DS33Z41 provides a single MII
Management port, and all control registers for this function are located in MAC 1.
Figure 8-11. MII Management Frame
8.15 BERT
The BERT can be used for generation and detection of BERT patterns. The BERT is a software programmable
test pattern generator and monitor capable of meeting most error performance requirements for digital
transmission equipment. The following restrictions are related to the BERT:
The transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data
stream. The receive direction extracts the test pattern payload from the receive data stream, and monitors the test
pattern payload for the programmable test pattern.
8.15.1 BERT Features
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The user should provide a gapped clock on RCLKI and TCLKI that is active during channels in which the
user wishes to insert the BERT pattern. Several of the Dallas Semiconductor Framers and Transceivers
provide programmable channel blocking pins for this purpose.
BERT will transmit even when the device is set for X.86 mode.
The normal traffic flow is halted while the BERT is in operation.
If the BERT is enabled for a Serial port, it will override the normal connection.
If there is a connection overridden by the BERT, when BERT operation is terminated the normal
operation is restored.
PRBS and QRSS patterns of 2
Programmable repetitive pattern. The repetitive pattern length and pattern are programmable (length n =
1 to 32 and pattern = 0 to (2
24-bit error count and 32-bit bit count registers.
Programmable bit error insertion. Errors can be inserted individually.
READ
WRITE
Preamble
111...111
111...111
32 bits
Figure
8-11. The read/write control of the MII Management is accomplished through the
2 bits
Start
01
01
n
Opco
2 bits
de
10
01
– 1).
9
-1, 2
Phy Adrs
PHYA[4:0]
PHYA[4:0]
15
5 bits
-1, 2
23
-1, and QRSS pattern support.
48 of 167
PHYR[4:0]
PHYR[4:0]
Phy Reg
5 bits
Aroun
2 bits
Turn
ZZ
10
d
ZZZZZZZZZ
PHYD[15:0]
bits
Data
16
Idle
Bit
1
Z
Z
Table
8-8.