DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 27

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3 Resets and Low-Power Modes
The external RST pin and the global reset bit in
signal resets the status and control registers on the chip (except the
resets all the other flops to their reset values. The device should be reset after all power supplies, SYSCLKI,
RX_CLK, and TX_CLK are stable. The processor bus output signals are also placed in high-impedance mode
when the RST pin is active (low). The global reset bit
reset to zero when the external RST pin is active or when a zero is written to it. Allow 5ms after initiating a reset
condition for the reset operation to complete.
The Serial Interface reset bit in
default values, except for the LI.RSTPD.RST bit. The Serial Interface includes the HDLC encoder/decoder, X86
encoder and decoder and the corresponding serial port. The Serial Interface reset bit (LI.RSTPD.RST) stays set
after a one is written to it, but is reset to zero when the global reset signal is active or when a zero is written to it.
Table 8-2. Reset Functions
Hardware Device Reset
Hardware JTAG Reset
Global Software Reset
Serial interface Reset
Queue Pointer Reset
There are several features in the DS33Z41 to reduce power consumption. The reset bit in the
minimizes power usage in the Serial Interface. Additionally, the RST pin or GL.CR1.RST bit may be held in reset
indefinitely to keep the device in a low-power mode. Note that exiting a reset condition requires re-initialization
and configuration. For the lowest possible standby current, clocks may be externally gated.
RESET FUNCTION
LI.RSTPD
LOCATION
GL.C1QPR
JTRST Pin
LI.RSTPD
RST Pin
GL.CR1
resets all the status and control registers on the Serial Interface to their
GL.CR1
27 of 167
(GL.CR1.
Transition to a logic 0 level resets the
device.
Resets the JTAG test port.
Writing to this bit resets the device.
Writing to this bit resets a Serial
Interface.
Writing to this bit resets the Queue
Pointers.
create an internal global reset signal. The global reset
RST) stays set after a one is written to it, but is
GL.CR1.
COMMENTS
RST bit) to their default values and
LI.RSTPD
register