DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 159

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12 JTAG INFORMATION
The device supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and EXTEST. Optional public
instructions included are HIGHZ, CLAMP, and IDCODE. The device contains the following as required by IEEE
1149.1 Standard Test Access Port and Boundary Scan Architecture.
The Test Access Port has the necessary interface pinsL: JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin
descriptions for details. Refer to IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994 for details
about the Boundary Scan Architecture and the Test Access Port.
Figure 12-1. JTAG Functional Block Diagram
Test Access Port (TAP)
TAP Controller
Instruction Register
10K
JTDI
10K
JTMS
Bypass
Register
Register
Register
Register
Controller
Instruction
Identification
Boundary Scan
Test Access Port
JTCLK
10K
JTRST
159 of 167
Select
Tri-State
Mux
JTDO
Bypass Register
Boundary Scan Register
Device Identification Register