DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 91

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Transmit Inter-Frame Gapping (TIFG7 to TIFG0). These eight bits indicate the number of additional
flags and bytes of inter-frame fill to be inserted between packets. The number of flags and bytes of inter-frame fill
between packets is at least the value of TIFG[7:0] plus 1. Note: If inter-frame fill is set to all ones, a TFIG value of
2 or 3 will result in a flag, two bytes of ones, and an additional flag between packets.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Transmit Errored Packet Insertion Number (TPEN7 to TPEN0). These eight bits indicate the total
number of errored packets to be transmitted when triggered by TIAEI. Error insertion will end after this number of
errored packets have been transmitted. A value of FFh results in continuous errored packet insertion at the
specified rate.
TPEN7
TIFG7
7
0
7
0
TPEN6
TIFG6
6
0
6
0
LI.TIFGC
Transmit Inter-Frame Gapping Control Register
0C5h
LI.TEPLC
Transmit Errored Packet Low Control Register
0C6h
TPEN5
TIFG5
5
0
5
0
TPEN4
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TIFG4
4
0
4
0
TPEN3
TIFG3
3
0
3
0
TPEN2
TIFG2
2
0
2
0
TPEN1
TIFG1
1
0
1
0
TPEN0
TIFG0
0
1
0
0