DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 115

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: MAC Write Address (MACAW15 to MACAW8). High byte of the MAC address. Used only for write
operations.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 1: MAC Command RW (MCRW). If this bit is written to 1, a read is performed from the MAC. If this bit is
written to 0, a write operation is performed. Address information for write operations must be located in
SU.MACAWH
SU.MACRADL. The user must also write a 1 to the MCS bit, and the DS33Z41 will clear MCS when the operation
is complete.
Bit 0: MAC Command Status (MCS). Setting MCS in conjunction with MCRW will initiate a read or write to the
MAC registers. Upon completion of the read or write this bit is cleared. Once a read or write command has been
initiated the host must poll this bit to see when the operation is complete.
MACAW 15
and SU.MACAWL. Address information for read operations must be located in
—
7
0
7
0
MACAW 14
—
6
0
6
0
SU.MACAWH
MAC Address Write High
14Bh
SU.MACRWC
MAC Read Write Command Status
14Ch
MACAW 13
—
5
0
5
0
MACAW12
115 of 167
—
4
0
4
0
MACAW11
—
3
0
3
0
MACAW10
—
2
0
2
0
MACAW9
MCRW
1
0
1
0
SU.MACRADH
MACAW8
MCS
0
0
0
0
and