DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 89

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.5 Serial Interface Registers
The Serial Interface contains the Serial HDLC transport circuitry and the associated serial port. The Serial
Interface register map consists of registers that are common functions, transmit functions, and receive functions.
Bits that are underlined are read-only; all other bits can be written. All reserved registers and bits with “-“
designation should be written to zero, unless specifically noted in the register definition. When read, the
information from reserved registers and bits designated with “-“ should be discarded.
Counter registers are updated by asserting (low to high transition) the associated performance monitoring update
signal (xxPMU). During the counter register update process, the associated performance monitoring status signal
(xxPMS) is deasserted. The counter register update process consists of loading the counter register with the
current count, resetting the counter, forcing the zero count status indication low for one clock cycle, and then
asserting xxPMS. No events are missed during this update procedure.
A latched bit is set when the associated event occurs, and remains set until it is cleared by reading. Once cleared,
a latched bit will not be set again until the associated event occurs again. Reserved configuration bits and
registers should be written to zero.
9.5.1
Serial Interface Transmit Registers are used to control the HDLC transmitter associated with each Serial
Interface. The register map is shown in the following Table. Note that throughout this document the HDLC
Processor is also referred to as a “packet processor”.
9.5.2
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 1: Reset (RESET). If this bit set to 1, the Data Path and Control and Status for this interface are reset. The
Serial Interface is held in Reset as long as this bit is high. This bit must be high for a minimum of 200ns for a valid
reset to occur.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Queue Loopback Enable (QLP). If this bit set to 1, data received on the Serial Interface is looped back to
the Serial Interface transmitter. Received data will not be sent from the Serial Interface to the Ethernet Interface.
Buffered packet data will remain in queue until the loopback is removed.
Serial Interface Transmit and Common Registers
Serial Interface Transmit Register Bit Descriptions
—
—
7
0
7
0
—
—
6
0
6
0
LI.RSTPD
Serial Interface Reset Register
0C1h
LI.LPBK
Serial Interface Loopback Control Register
0C2h
—
—
5
0
5
0
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—
—
4
0
4
0
—
—
3
0
3
0
—
—
2
0
2
0
RESET
—
1
0
1
0
QLP
—
0
0
0
0