DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 79

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 0: BIST Pass-Fail (BISTPF). This bit is equal to 0 after the DS33Z41 performs BIST testing on the SDRAM
and the test passes. This bit is set to 1 if the test failed. This bit is valid only after the BIST test is complete and
the BIST DN bit is set. If set this bit can only be cleared by resetting the DS33Z41.
Register Name:
Register Description:
Register Address:
Bit 3: Wrap Type (WT). This bit is used to configure the wrap mode.
Bits 2 to 0: Burst Length 2 to 0 (BL2 to BL0). These bits are used to determine the burst length.
Note: This register has a non-zero default value. This should be taken into consideration when initializing
the device.
Note: After changing the value of this register, the user must toggle the GL.SDMODEWS.SDMW bit to
write the new values to the SDRAM.
Register Name:
Register Description:
Register Address:
Bits 2 to 0: CAS Latency Mode (LTMOD2 to LTMOD0). These bits are used to set up CAS latency. Note: Only
CAS latency of 2 or 3 is allowed.
Note: This register has a non-zero default value. This should be taken into consideration when initializing
the device.
Note: After changing the value of this register, the user must toggle the GL.SDMODEWS.SDMW bit to
write the new values to the SDRAM.
Register Name:
Register Description:
Register Address:
Bit 0: SDRAM Mode Write (SDMW). Setting this bit to 1 will write the current values of the mode control and
refresh time control registers to the SDRAM. The user must clear this bit and set it again for subsequent write
operations.
Bit #
Name
Default
Bit #
Name
Default
Bit #
Name
Default
—
—
7
0
7
0
—
7
0
0 = Sequential
1 = Interleave
—
—
6
0
6
0
—
6
0
GL.SDMODE1
Global SDRAM Mode Register 1
3Ah
GL.SDMODE2
Global SDRAM Mode Register 2
3Bh
Global SDRAM Mode Register Write Status
3Ch
GL.SDMODEWS
—
—
5
0
5
0
—
5
0
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—
—
4
0
4
0
—
4
0
WT
—
—
3
0
3
0
3
0
LTMOD2
BL2
—
0
0
2
2
2
0
LTMOD1
BL1
—
1
1
1
1
1
0
LTMOD0
SDMW
BL0
0
1
0
0
0
0