DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 72

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 4: Transmit Queue 1 Interrupt Enable (TQ1IE). Setting this bit to 1 enables an interrupt on TQ1IS.
Bit 0: Receive Queue 1 Interrupt Enable (RQ1IE). Setting this bit to 1 enables an interrupt on RQ1IS.
Register Name:
Register Description:
Register Address:
Bit 4: Transmit Queue 1 Interrupt Enable (TQ1IS). If this bit is set to 1, the Transmit Queue 1 has interrupt
status event. Transmit queue events are transmit queue crossing thresholds and queue overflows.
Bit 0: Receive Queue 1 Interrupt Status (RQ1IS). If this bit is set to 1, the Receive Queue 1 has interrupt status
event. Receive queue events are transmit queue crossing thresholds and queue overflows.
Bit 1: IMUX Interrupt Enable (IMUXIE). Setting this bit to 1 enables an interrupt on IIS.
Bit 0: BERT Interrupt Enable (BIE). Setting this bit to 1 enables an interrupt on BIS.
Bit 1: IMUX Interrupt Status (IIS). This bit is set to 1 if the IMUX has an enabled interrupt generating event.
Bit 0: BERT Interrupt Status (BIS). This bit is set to 1 if the BERT has an enabled interrupt generating event.
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
—
—
—
—
7
0
7
0
7
0
7
0
—
—
—
—
6
0
6
0
6
0
6
0
GL.TRQIS
Global Transmit Receive Queue Interrupt Status
0Bh
GL.TRQIE
Global Transmit Receive Queue Interrupt Enable
GL.IBIE
Global IMUX and BERT Interrupt Enable
0Ch
GL.IBIS
Global IMUX and BERT Interrupt Status
0Dh
0Ah
—
—
—
—
5
0
5
0
5
0
5
0
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TQ1IS
TQ1IE
—
—
4
0
4
0
0
4
4
0
—
—
—
—
3
0
3
0
3
0
3
0
—
—
—
—
2
0
2
0
2
0
2
0
IMUXIE
IIS
—
—
1
0
1
0
1
0
1
0
RQ1IE
RQ1IS
BIE
BIS
0
0
0
0
0
0
0
0