DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 110

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 3: SAPI Octet Not Equal to
LI.RX86S.SAPIHNE will generate an interrupt.
Bit 2: SAPI Octet Not Equal to
LI.RX86S.SAPILNE will generate an interrupt.
Bit 1: Control Not Equal to
generate an interrupt.
Bit 0: Address Not Equal to
generate an interrupt.
Bits 7 to 0: Transmit Queue Low Threshold (TQLT7 to TQLT0). The transmit queue low threshold for the
connection, in increments of 32 packets of 2048 bytes each. The value of this register is multiplied by 32 * 2048
bytes to determine the byte location of the threshold. Note that the transmit queue is for data that was received
from the Serial Interface to be sent to the Ethernet Interface.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
TQLT7
—
7
0
7
0
—
6
0
TQLT6
6
0
LI.TRX8C
LI.TRX86A
LI.RX86LSIE
Receive X.86 Interrupt Enable
123h
LI.TQLT
Serial Interface Transmit Queue Low Threshold (Watermark)
124h
—
5
0
LI.TRX86SAPIH
LI.TRX86SAPIL
TQLT5
Interrupt Enable (CNE3LIM). If this bit is set to 1, LI.RX86S.CNE will
5
0
Interrupt Enable (ANE4IM). If this bit is set to 1, LI.RX86S.ANE will
—
4
0
110 of 167
TQLT4
Interrupt Enable (SAPINEFEIM). If this bit is set to 1,
Interrupt Enable (SAPINE01IM). If this bit is set to 1,
4
0
SAPINE01IM
3
0
TQLT3
3
0
SAPINEFEIM
TQLT2
2
0
2
0
CNE3LIM
TQLT1
1
0
1
0
ANE4IM
TQLT0
0
0
0
0