DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 18

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SDATA[10]
SDATA[11]
SDATA[12]
SDATA[13]
SDATA[14]
SDATA[15]
SDATA[16]
SDATA[17]
SDATA[18]
SDATA[19]
SDATA[20]
SDATA[21]
SDATA[22]
SDATA[23]
SDATA[24]
SDATA[25]
SDATA[26]
SDATA[27]
SDATA[28]
SDATA[29]
SDATA[30]
SDATA[31]
SDATA[0]
SDATA[1]
SDATA[2]
SDATA[3]
SDATA[4]
SDATA[5]
SDATA[6]
SDATA[7]
SDATA[8]
SDATA[9]
SDA[10]
SDA[11]
SDA[0]
SDA[1]
SDA[2]
SDA[3]
SDA[4]
SDA[5]
SDA[6]
SDA[7]
SDA[8]
SDA[9]
SBA[0]
SBA[1]
NAME
SRAS
M12
M11
H11
N13
N11
N12
H13
H12
G12
G11
N10
PIN
K13
F11
K11
L13
J13
J12
L10
L11
M1
M2
M3
M5
M7
M8
M6
N1
N2
N4
N3
H3
K1
K2
N9
N8
N7
K6
L2
L4
L1
L7
L8
L9
L5
J3
J1
J2
TYPE
IOZ
O
O
I
SDRAM Data Bus Bits 0 to 31: The 32 pins of the SDRAM data bus
are inputs for read operations and outputs for write operations. At all
other times, these pins are high impedance.
Note: All SDRAM operations are controlled entirely by the DS33Z41.
No user programming for SDRAM buffering is required.
SDRAM Address Bus 0 to 11. The 12 pins of the SDRAM address bus
output the row address first, followed by the column address. The row
address is determined by SDA0 to SDA11 at the rising edge of clock.
Column address is determined by SDA0-SDA9 and SDA11 at the rising
edge of the clock. SDA10 is used as an auto-precharge signal.
Note: All SDRAM operations are controlled entirely by the DS33Z41.
No user programming for SDRAM buffering is required.
SDRAM Bank Select. These 2 bits select 1 of 4 banks for the
read/write/precharge operations.
Note: All SDRAM operations are controlled entirely by the DS33Z41.
No user programming for SDRAM buffering is required.
SDRAM Row Address Strobe. Active-low output, used to latch the row
address on rising edge of SDCLKO. It is used with commands for Bank
Activate, Precharge, and Mode Register Write.
SDRAM CONTROLLER
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FUNCTION