DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 60

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9 DEVICE REGISTERS
Ten address lines are used to address the register space.
The addressable range for the device is 0000h to 08FFh. Each Register Section is 64 bytes deep. Global
Registers are preserved for software compatibility with multiport devices. The Serial Interface (Line) Registers are
used to configure the serial port and the associated transport protocol. The Ethernet Interface (Subscriber)
registers are used to control and observe the Ethernet port. The registers associated with the MAC must be
configured through indirect register write /read access due to the architecture of the device.
When writing to a register input values for unused bits and registers (those designated with “–“) should be zero
unless specifically noted otherwise, as these bits and registers are reserved. When a register is read from, the
values of the unused bits and registers should be ignored. A latched status bit is set when an event happens and
is cleared when read.
The register details are provided in the following tables.
Table 9-1. Register Address Map
Port 1
Reserved address space: 0180h - 07FFh.
0000h – 003Fh
Global Registers
-
0040h – 007Fh
Arbiter
-
0080h – 00BFh
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BERT
Table 9-1
-
shows the register map for the DS33Z41.
00C0h – 013Fh
Serial Interface
-
0140h – 017Fh
Interface
Ethernet
-