DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 75

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: IMUX Transmit Sync 4 (ITSYNC4). If this bit is set to 1, the device has received a rsync command for the
4
Bit 6: IMUX Transmit Sync 3 (ITSYNC3). If this bit is set to 1, the device has received a rsync command for the
3
Bit 5: IMUX Transmit Sync 2 (ITSYNC2). If this bit is set to 1, the device has received a rsync command for the
2
Bit 4: IMUX Transmit Sync 1 (ITSYNC1). If this bit is set to 1, the device has received a rsync command for the
1
Bit 3: IMUX Receive Sync 4 (IRSYNC4). If this bit is set to 1, the local end is in sync for the 4
8.192Mbps link. The command states that the local end is in sync.
Bit 2: IMUX Receive Sync 3 (IRSYNC3). If this bit is set to 1, the local end is in sync for the 3
8.192Mbps link. The command states that the local end is in sync.
Bit 1: IMUX Receive Sync 2 (IRSYNC2). If this bit is set to 1, the local end is in sync for the 2
8.192Mbps link. The command states that the local end is in sync.
Bit 0: IMUX Receive Sync 1 (IRSYNC1). If this bit is set to 1, the local end is in sync for the 1
8.192Mbps link. The command states that the local end is in sync.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: IMUX Transmit Sync Interrupt Enable 4 (ITSYNCIE4). Setting this bit to 1 enables an interrupt on
ITSYNCLS4.
Bit 6: IMUX Transmit Sync Interrupt Enable 3 (ITSYNCIE3). Setting this bit to 1 enables an interrupt on
ITSYNCLS3.
Bit 5: IMUX Transmit Sync Interrupt Enable 2 (ITSYNCIE2). Setting this bit to 1 enables an interrupt on
ITSYNCLS2.
Bit 4: IMUX Transmit Sync Interrupt Enable 1 (ITSYNCIE1). Setting this bit to 1 enables an interrupt on
ITSYNCLS1.
Bit 3: IMUX Receive Sync Interrupt Enable 4 (IRSYNCIE4). Setting this bit to 1 enables an interrupt on
IRSYNCLS4.
Bit 2: IMUX Receive Sync Interrupt Enable 3 (IRSYNCIE3). Setting this bit to 1 enables an interrupt on
IRSYNCLS3.
Bit 1: IMUX Receive Sync Interrupt Enable 2 (IRSYNCIE2). Setting this bit to 1 enables an interrupt on
IRSYNCLS2.
Bit 0: IMUX Receive Sync Interrupt Enable 1 (IRSYNCIE1). Setting this bit to 1 enables an interrupt on
IRSYNCLS1.
th
rd
nd
st
portion of the 8.192Mbps link from the distant node. This status bit indicates that the distant end is in sync.
portion of the 8.192Mbps link from the distant node. This status bit indicates that the distant end is in sync.
portion of the 8.192Mbps link from the distant node. This status bit indicates that the distant end is in sync.
portion of the 8.192Mbps link from the distant node. This status bit indicates that the distant end is in sync.
ITSYNCIE4
ITSYNC4
7
0
7
0
ITSYNC3
ITSYNCIE3
6
0
6
0
GL.IMXSS
Inverse MUX Sync Status
18h
GL.IMXSIE
Inverse Mux Sync Interrupt Enable
19h
ITSYNC2
ITSYNCIE2
5
0
5
0
ITSYNC1
ITSYNCIE1
75 of 167
4
0
4
0
IRSYNC4
IRSYNCIE4
3
0
3
0
IRSYNCIE3
IRSYNC3
2
0
2
0
IRSYNC2
IRSYNCIE2
1
0
1
0
nd
rd
th
st
portion of the
portion of the
portion of the
portion of the
IRSYNC1
IRSYNCIE1
0
0
0
0