DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 24

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.2 Clock Structure
The DS33Z41 clocks sources and functions are as follows:
The following table provides the different clocking options for the Ethernet interface.
Table 8-1. Clock Selection for the Ethernet (LAN) Interface
RMIIMIIS
1 (RMII)
1 (RMII)
0 (MII)
0 (MII)
0 (MII)
PIN
•
•
•
•
•
•
Serial Transmit Data (TCLKI) and Serial Receive Data (RCLKI) clock inputs are used to transfer data from
the serial interface. These clocks can be gapped.
System Clock (SYSCLKI) input. Used for internal operation. This clock input cannot be a gapped clock. A
clock supply with ±100ppm frequency accuracy is suggested. A buffered version of this clock is provided
on the SDCLKO pin for the operation of the SDRAM. A divided and buffered version of this clock is
provided on REF_CLKO for the RMII/MII interface.
Packet Interface Reference clock (REF_CLK) input that can be 25MHz or 50MHz. This clock is used as
the timing reference for the RMII/MII interface.
The Transmit and Receive clocks for the MII Interface (TX_CLK and RX_CLK). In DTE mode, these are
input pins and accept clocks provided by an Ethernet PHY. In the DCE mode, these are output pins and
will output an internally generated clock to the Ethernet PHY. The output clocks are generated by internal
division of REF_CLK. In RMII mode, only the REF_CLK input is used.
REF_CLKO is an output clock that is generated by dividing the 100MHz System clock (SYSCLKI) by 2 or
4.
A Management Data Clock (MDC) output is derived from SYSCLKI and is used for information transfer
between the internal Ethernet MAC and external PHY. The MDC clock frequency is 1.67MHz.
SPEED
(Mbps)
10
10
10
10
10
DCE/
DCE
DCE
DTE
DTE
—
—
REF_CLKO
OUTPUT
(MHz)
25
50
50
25
25
REF_CLK
±100ppm
±100ppm
±100ppm
±100ppm
±100ppm
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25MHz
25MHz
25MHz
50MHz
50MHz
INPUT
Not Applicable
Not Applicable
Input from
RX_CLK
(Output)
(Output)
2.5MHz
25MHz
PHY
Not Applicable
Not Applicable
Input from
TX_CLK
(Output)
(Output)
2.5MHz
25MHz
PHY
OUTPUT
(MHz)
MDC
1.67
1.67
1.67
1.67
1.67