DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 9
DS33Z41
Manufacturer Part Number
DS33Z41
Description
Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33Z41.pdf
(167 pages)
Specifications of DS33Z41
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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2.6 SDRAM Interface
2.7 MAC Interface
2.8 Microprocessor Interface
2.9 Test and Diagnostics
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Interface for 128Mb, 32-bit-wide SDRAM
SDRAM Interface speed up to 100MHz
Auto Refresh Timing
Automatic Precharge
Master clock provided to the SDRAM
No external components required for SDRAM connectivity
MAC port with standard MII (less TX_ER) or RMII
10Mbps and 100Mbps Data rates
Configurable DTE or DCE modes
Facilitates auto-negotiation by host microprocessor
Programmable half and full-duplex modes
Flow control for both half-duplex (back-pressure) and full-duplex (PAUSE) modes
Programmable Maximum MAC frame size up to 2016 bytes
Minimum MAC frame size: 64 bytes
Discards frames greater than Programmed Maximum MAC frame size and Runt, non-octet bounded,
or bad-FCS frames upon reception
Programmable threshold for SDRAM queues to initiate flow control and status indication
MAC Loopback support for Transmit data looped to Receive Data at the MII/RMII interface
8 bit data bus
Non-multiplexed Intel and Motorola Timing Modes
Internal software reset and External Hardware reset input pin
Global interrupt output pin
IEEE 1149.1 Support
Programmable on-chip Bit Error Rate Tester (BERT)
Patterns include Pseudorandom QRSS, Daly, and user-defined repetitive patterns
Loopbacks (remote, local, analog, and per-channel loopback)
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