DS33Z41 Maxim Integrated Products, DS33Z41 Datasheet - Page 122

• Manufacturer Part Number: DS33Z41
• Description: Network Controller & Processor ICs Quad Inverse-Multipl exing Ethernet Mappe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z41

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 3: Receive FIFO Overflow Interrupt Enable (RFOVFIE). If this bit is set, the interrupt is enabled for
RFOVFLS.
Bit 2: Receive Queue Overflow Interrupt Enable (RQVFIE). If this bit is set, the interrupt is enabled for
RQOVFLS.
Bit 1: Receive Queue Crosses Low Threshold Interrupt Enable (RQLTIE). If this bit is set, the watermark
interrupt is enabled for RQLTS.
Bit 0: Receive Queue Crosses High Threshold Interrupt Enable (RQHTIE). If this bit is set, the watermark
interrupt is enabled for RQHTS.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 3: Receive FIFO Overflow latched Status (RFOVFLS). This bit is set if the receive FIFO overflows for the
data to be transmitted from the MAC to the SDRAM.
Bit 2: Receive Queue Overflow Latched Status (RQOVFLS). This bit is set if the receive queue has
overflowed. This register is cleared after a read.
Bit 1: Receive Queue for Connection Crossed High Threshold Latched Status (RQHTLS). This bit is set if
the receive queue crosses the high watermark. This register is cleared after a read.
Bit 0: Receive Queue for Connection Crossed Low Threshold Latched Status (RQLTLS). This bit is set if the
receive queue crosses the low watermark. This register is cleared after a read.
Note the bit order differences in the high/low threshold indications in SU.QCRLS and the interrupt enables in
SU.QRIE.
—
—
—
7
7
0
—
—
6
—
6
0
SU.QRIE
Receive Queue Cross Threshold Enable
15Ch
SU.QCRLS
Queue Cross Threshold Latched Status
15Dh
—
—
5
—
5
0
—
—
4
122 of 167
—
4
0
RFOVFLS
RFOVFIE
—
3
3
0
RQOVFLS
RQVFIE
—
2
2
0
RQHTLS
RQLTIE
—
1
1
0
RQLTLS
RQHTIE
—
0
0
0