Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 10

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35 ISCC™ User’s Manual
General Description
1.3 PIN DESCRIPTION (Continued)
When the ISCC is the bus master (the DMA cell has taken
control of the bus), the /Wait//RDY signal functions as a
/WAIT or /READY input. Slow memories and peripheral
devices can assert /WAIT to extend /DS during bus trans-
fers. Similarly, memories and peripherals use /READY to
indicate that its output is valid or that it is ready to latch in-
put data.
/BUSACK. Bus Acknowledge (input, active Low). Signals
the bus has been released to the DMA. If the /BUSACK
goes inactive before the DMA transfer is completed, the
current DMA transfer is aborted.
/BUSREQ. Bus Request (output, active Low). This signal
is used by the DMA to obtain the bus from the CPU.
A0/SCC//DMA. DMA Channel/SCC Select/DMA Select
(bidirectional). When this pin is used as input, a high se-
lects the SCC cell and a low selects the DMA cell, (during
BCR Write should be kept Low). When this pin is used as
output, the signal on this pin is used in conjunction with
A1/A//B pin output to identify which DMA channel is active.
This information can be used by the user to determine
whether to issue a DMA abort command. A0/SCC//DMA
and A1/A//B output encoding is shown on the following
page.
1-8
A1/A//B. DMA Channel/Channel A/Channel B (bidirection-
al). This signal, when used as input, selects the SCC chan-
nel in which the read and write operation occurs. Note that
A0/SCC//DMA pin must be held high to select this feature.
When this pin is used as an output, it is used in conjunction
with the A0/SCC//DMA pin output to identify which DMA
channel is active. During a DMA peripheral access, the
A1/A//B pin is ignored.
/RESET. (input, active Low). This signal resets the device
to a known state. The first write to the ISCC after a reset
accesses the BCR to select additional bus options for the
device.
A1/A//B
1
1
0
0
A0/SCC//DMA
1
0
1
0
UM011001-0601
DMA channel
RxA
RxB
TxA
TxB