Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 69

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
Bit 3 is the Receiver CRC Enable
This bit is used to initiate CRC calculation at the beginning
of the last byte transferred from the Receiver Shift register
to the receive FIFO. This operation occurs independently
of the number of bytes in the receive FIFO. When a partic-
ular byte is to be excluded from CRC calculation, this bit
should be reset before the next byte is transferred to the
receive FIFO. If this feature is used, care must be taken to
ensure that eight bits per character is selected in the re-
ceiver because of an inherent delay from the Receive Shift
register to the CRC checker.
This bit is internally set to “1” in SDLC mode and the ISCC
calculates CRC on all bits except inserted zeros between
the opening and closing character flags. This bit is ignored
in asynchronous modes.
Bit 2 selects the Address Search Mode (SDLC)
Setting this bit in SDLC mode causes messages with ad-
dresses not matching the address programmed in WR6 to
be rejected. No receiver interrupts can occur in this mode
unless there is an address match. The address that the
ISCC attempts to match can be unique (1 in 256) or multi-
ple (16 in 256), depending on the state of Sync Character
Load Inhibit bit. The Address Search mode bit is ignored in
all modes except SDLC.
Bit 1 is the SYNC Character Load Inhibit
If this bit is set to “1” in any mode except SDLC, the ISCC
compares the byte in WR6 with the byte about to be stored
in the FIFO, and it inhibits this load if the bytes are equal.
(Caution this also occurs in the asynchronous mode if the
received character matches the contents of WR6.) The
ISCC does not calculate the CRC on bytes stripped from
the data stream in this manner. If the 6-bit sync option is
selected while in Monosync mode, the compare is still
across eight bits, so WR6 must be programmed for proper
operation.
If the 6-bit sync option is selected with this bit set to “1,” all
sync characters except the one immediately preceding the
data are stripped from the message. If the 6-bit sync option
is selected while in the Bisync mode, this bit is ignored.
The address recognition logic of the receiver is modified in
SDLC mode if this bit is set to “1,” i.e. only the four most
significant bits of WR6 must match the receiver address.
This procedure allows the ISCC to receive frames from up
to 16 separate sources without programming WR6 for
each source (if each station address has the four most sig-
nificant bits in common). The address field in the frame is
still eight bits long.
The bit is ignored in SDLC mode if Address Search mode
has not been selected.
P R E L I M I N A R Y
Bit 0 is the Receiver Enable
When this bit is set to “1,” receiver operation begins. This
bit should be set only after all other receiver parameters
are established and the receiver is completely initialized.
This bit is reset by a channel or hardware reset command,
and it disables the receiver.
5.4.5 Write Register 4 (Transmit/Receiver
Miscellaneous Parameters and Modes)
WR4 contains the control bits for both the receiver and the
transmitter. These bits should be set in the transmit and re-
ceiver initialization routine before issuing the contents of
WR1, WR3, WR6, and WR7. Bit positions for WR4 are
shown in Figure 5-6.
Bit 7 and 6 are the Clock Mode, Bits 1 And 0
These bits specify the multiplier between the clock and
data rates. In synchronous modes, the 1X mode is forced
internally and these bits are ignored unless External Sync
mode has been selected.
Bit combination 00 selects the 1X Mode. The clock rate
and data rate are the same. In External Sync mode, this bit
combination specifies that only the /SYNC pin can be used
to achieve character synchronization.
Write Register 4
D7
0
0
1
1
D6
0
1
0
1
D5 D4 D3 D2 D1 D0
0
0
1
1
X1 Clock Mode
X16 Clock Mode
X32 Clock Mode
X64 Clock Mode
Figure 5-6. Write Register 4
0
1
0
1
0
0
1
1
8-Bit Sync Character
16-Bit Sync Character
SDLC Mode (01111110 Flag)
External Sync Mode
0
1
0
1
Z16C35ISCC™ User’s Manual
Sync Modes Enable
1 Stop Bit/Character
1 1/2 Stop Bits/Character
2 Stop Bits/Character
Register Descriptions
Parity Enable
Parity EVEN/ODD
5-9
5