Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 219

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
AUTOMATIC /RTS DEASSERTION
Several SDLC enhancements are provided in the ESCC.
The ESCC allows automatic /RTS deassertion at End Of
Frame (EOF). The automatic /RTS deassertion is enabled
by setting WR7' D2. If ESCC is programmed for SDLC
mode and the Flag-On-Underrun bit (WR10 D2) is reset,
with the RTS bit (WR5 D1) reset, /RTS is deasserted
automatically at the last bit of the closing flag. It is triggered
by the rising edge of the Transmit Clock (TxC - Figures 6
and 7).
TXC
TXD
/RTS
TX Underrun/EOM
(WR5, D1)
/RTS Pin
RTS Bit
Automatic RTS Pin Deactivation
Figure 7. /RTS Deassertion Sequence
Figure 6. /RTS Deassertion Timing
TX Closing
Flag
Data Being Sent
Data
Boost Your System Performance Using The Zilog ESCC
CRC1
/RTS is normally used in SDLC for switching the direction
of line drivers. Automatic /RTS deassertion allows optimal
line switching without any software intervention. The
typical procedures are as follows:
1. Enable Automatic /RTS Deassertion
2. Before frame transmission, set RTS bit
3. Enable frame transmission
4. Reset RTS bit
5. RTS pin deassertion is delayed until the last rising TxC
edge closing flag.
CRC2
Flag
Mark
Application Note
13-7
™
1