Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 198

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Application Note
Serial Communication Controller (SCC
THE SDLC LOOP MODE
The SDLC Loop mode is one of the protocols used in the
ring configuration network topology. The typical network
configuration is shown in Figure 5. As shown, there is one
Master (or primary) station and several slave (or
secondary) stations. This figure does not have a clock
This mode is similar to the normal SDLC mode, other than
that secondary stations are not allowed to freely send out
packets. When a secondary station wants to send a
packet, it needs to wait for a special pattern to be received.
The pattern is called EOP (End Of Poll), and consists of a
0 followed by seven 1s on the transmission line (as data, it
is 11111110). This pattern resembles the SDLC Flag
pattern (7EH; 0111110), except the last bit has been
changed to a 1 thus turning this pattern into a flag.
Upon network initialization, secondary station TxD and
RxD connections use gate propagation delay. On the first
EOP, a secondary station inserts one bit -time delay
between RxD and TxD, and relays RxD input to TxD.
11-10
Slave SCC #1
Rx
Tx
Figure 5. SDLC Loop Mode Configuration
™
): SDLC Mode of Operation
Slave SCC #2
Rx
Master SCC
Tx
connection, but each station’s transmit clock must be
synchronized to the master SCC. This can be done by
feeding the clock using a separate clock line, or by using
Phase Locked Loop (PLL) to recover the clock.
When it has a message to send out, it waits for an EOP.
When it detects EOP in this phase, it changes the last bit
of the EOP to zero, making it a Flag, then begins to send
its own message. From this point on, normal SDLC
transmission modes apply. Packets conclude with Mark
idle, identifying it as an EOP pattern. The secondary
station then reverts back to one bit delay mode.
Figure 6 illustrates this mode’s sequence of events. To
simplify the example, this figure assumes there is one
Master station and one Slave station. If there are more
Slave stations, there will be additional one bit time delay
per station after the network has initialized for loop mode
of operation.
Rx
Tx
Slave SCC #n
Rx
Tx
UM011001-0601