Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 68

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35ISCC™ User’s Manual
Register Descriptions
5.4 WRITE REGISTERS (Continued)
5.4.4 Write Register 3 (Receive Parameters and Control)
This register contains the control bits and parameters for
the receiver logic as illustrated in Figure 5-5.
Bit 7 and 6 select the Receiver Bits/Character
The state of these two bits determines the number of bits
to be assembled as a character in the received serial data
stream. The number of bits per character can be changed
while a character is being assembled but only before the
number of bits currently programmed is reached. Unused
bits in the Received Data Register (RR8) are set to “1” in
asynchronous modes. In synchronous modes and SDLC
modes, the ISCC merely transfers an 8-bit section of the
serial data stream to the receive FIFO at the appropriate
time. Table 5-5 lists the number of bits per character in the
assembled character format.
5-8
D7
0
0
1
1
Table 5-5. Receive Bits per Character
D6
0
1
0
1
Write Register 3
D7
0
0
1
1
D6
0
1
0
1
Bits/Character
5
7
6
8
D5 D4 D3 D2 D1 D0
Rx 5 Bits/Character
Rx 7 Bits/Character
Rx 6 Bits/Character
Rx 8 Bits/Character
Figure 5-5. Write Register 3
P R E L I M I N A R Y
Bit 5 selects Auto Enables
This bit programs the function for both the /DCD and /CTS
pins. /CTS becomes the transmitter enable and /DCD be-
comes the receiver enable when this bit is set to “1.” How-
ever, the Receiver Enable and Transmit Enable bits must
be set before the /DCD and /CTS pins can be used in this
manner. When the Auto Enables bit is set to “0,” the /DCD
and /CTS pins are merely inputs to the corresponding sta-
tus bits in Read Register 0. The state of /DCD is ignored in
the Local Loopback mode. The state of /CTS is ignored in
both Auto Echo and Local Loopback modes.
Bit 4 forces the SCC cell to Enter Hunt Mode
This command forces the comparison of sync characters
or flags to assembled receive characters for the purpose
of synchronization. After reset, the ISCC cell automatically
enters the Hunt mode (except asynchronous). Whenever
a flag or sync character is matched, the Sync/Hunt bit in
Read Register 0 is reset and, if External/Status Interrupt
Enable is set, an interrupt sequence is initiated. The ISCC
automatically enters the Hunt mode when an abort condi-
tion is received or when the receiver is enabled.
Rx Enable
Sync Character Load Inhibit
Address Search Mode (SDLC)
Rx CRC Enable
Enter Hunt Mode
Auto Enables
UM011001-0601