Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 101

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
INPUT/OUTPUT CYCLES
Although Z8500 peripherals are designed to be as
universal as possible, certain timing parameters differ from
the standard Z80 timing. The following sections discuss
the I/O interface for each of the Z80 CPUs and the Z8500
peripherals. Figure 9 depicts logic for the Z80A CPU to
Z8500 peripherals (and Z80B CPU to Z8500A peripherals)
I/O interface as well as the Interrupt Acknowledge
interface. Figures 4 and 7 depict some of the logic used to
interface the Z80H CPU to the Z8500 and Z8500A
peripherals for the I/O and Interrupt Acknowledge
interfaces. The logic required for adding additional Wait
states into the timing flow is not discussed in the following
sections.
Z80A CPU to Z8500 Peripherals
No additional Wait states are necessary during the I/O
cycles, although additional Wait states can be inserted to
compensate for timing delays that are inherent in a
system. Although the Z80A timing parameters indicate a
negative value for data valid prior to /WR, this is a worse
than “worst case” value. This parameter is based upon the
longest (worst case) delay for data available from the
falling edge of the CPU clock minus the shortest (best
case) delay for CPU clock High to /WR low. The negative
value resulting from these two parameters does not occur
because the worst case of one parameter and the best
case of the other do not occur within the same device. This
indicates that the value for data available prior to /WR will
always be greater than zero.
All setup and pulse width times for the Z8500 peripherals
are met by the standard Z80A timing. In determining the
interface necessary, the /CE signal to the Z8500
peripherals is assumed to be the decoded address
qualified with the /IORQ signal.
Figure 4 shows the minimum Z80A CPU to Z8500
peripheral interface timing for I/O cycles. If additional Wait
states are needed, the same number of Wait states can be
inserted for both I/O Read and Write cycles to simplify
interface logic. There are several ways to place the Z80A
CPU into a Wait condition (such as counters or shift
registers to count system clock pulses), depending upon
whether or not the user wants to place Wait states in all
I/O cycles, or only during Z8500 I/O cycles. Tables 3 and
4 list the Z8500 peripheral and the Z80A CPU timing
parameters (respectively) of concern during the I/O cycles.
Tables 5 and 6 list the equations used in determining if
these parameters are satisfied. In generating these
equations and the values obtained from them, the required
number of Wait states was taken into account. The
reference numbers in Tables 3 and 4 refer to the timing
diagram in Figure 4.
Interfacing Z80
®
CPUs to the Z8500 Peripheral Family
Application Note
6-5
6