Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 231

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
Listing 1 (Reference Appendix A for Listings 1 through 4)
shows the assembler code for this SCC initialization. Note
that the SCC is treated as a peripheral by the Z80181’s
MPU. For example, an I/O write to the scc_cont (address
e8H) or to the scc_data (address e9H) is a write to the
SCC’s control and data registers, respectively. As shown
in Listing 1, the SCC is initialized by issuing I/O writes to
the pointer and then to the control registers in an
alternating fashion. It is therefore very important that all
interrupts are disabled during this initialization routine.
The SCC is initially reset through software before
proceeding to program the other write registers. A NOP is
sufficient to provide the four PCLKs required by the SCC
recovery time after a soft reset. The SCC is programmed
for SDLC mode. The receive, transmit and external
interrupts are all initially disabled during this initialization.
Each of these interrupt sources are enabled at their proper
times in the main program. The SCC is programmed to
include status information in the vector that it places on the
bus in response to an interrupt acknowledge cycle (see
Listing 4 of the SCC interrupt vector table for all the
possible sources).
7.37 MHz
1/2
Technical Considerations When Implementing LocalTalk Link Access Protocol
= 16x230.4 kHz
3.6864 MHz
/RTxC
Figure 3. SCC Clocking Scheme
/TRxC
/RTxC
Since SDLC is bit-oriented, the transmitter and receiver
are both programmed for 8 bits per character as required
by LLAP. Address filtering is implemented by setting the
Address Search Mode bit 2 on WR3. Setting this bit
causes messages with addresses not matching the
address programmed in WR6 and not matching the
broadcast address to be rejected. Values in WR10 presets
the CRCs to ones, sets the encoding to FM0 mode and
makes certain that transmission of flags occur during idle
and underrun conditions. WR11 is set so that the receive
clock is sourced by the DPLL output; the transmit clock is
sourced by the Baud Rate Generator output; /TRxC’s
output is from the BRG. The input to the BRG is from the
/RTxC.
The BRG’s time constant is loaded in WR13 and WR12 so
that the /RTxC’s 3.6864 MHz signal is divided by 16 in
order to obtain a 230.4 kHz signal for the transmitter clock.
WR14 makes certain that the DPLL is disabled before
choosing the clock source and operating mode. The DPLL
is enabled by issuing the Enter Search Mode in WR14.
DPLL
DPLL
BRG
/16
RxDPLL Out
BRG Out
230.4 kHz
Rx
Rx
Tx
Tx
Receiver
Transmitter
Application Note
14-5
1