Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 51

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
A specific sequence of operations must be followed to syn-
chronize the transmitter to the receiver. Both the receiver
and transmitter must have been initialized for operation in
Synchronous mode sometime in the past, although this ini-
tialization need not be redone each time the transmitter is
synchronized to the receiver. The transmitter is disabled
by setting bit D3 of WR5 to “0”. At this point the transmitter
will send continuous “1s”. If it is desired that continuous
“0s” be transmitted, the Send Break bit (D4) in WR5 should
be set to “1”. The transmitter is now idling but must still be
placed in the transmitter to receiver synchronization mode.
4.4 BIT-ORIENTED SYNCHRONOUS MODE
Synchronous Data Link Control mode (SDLC) uses syn-
chronization characters similar to Bisync and Monosync
modes (such as flags and pad characters), but it is a bit-
oriented protocol instead of byte-oriented protocol. High-
Level synchronous Data Link Communication (HDLC) pro-
tocol is identical to SDLC except for differences in framing
and can be handled by the ISCC using the SDLC mode.
The discussions on SDLC which follow are equally appli-
cable to HDLC.
Any data communication link involves at least two sta-
tions. The station that is responsible for the data link and
issues the commands to control the link is called the
Two flags that delineate the SDLC frame serve as refer-
ence points when positioning the address and control
fields, and they initiate the transmission error check. The
ending flag indicates to the receiving station that the 16-
bits just received constitute the frame check. The ending
flag could be followed by another frame, another flag, or an
idle. This means that when two frames follow one another,
the intervening flag may simultaneously be the ending flag
of the first frame and the beginning flag of the next frame.
Since the SDLC mode does not use characters of defined
length, but rather works on a bit-by-bit basis, the 01111110
(7EH) flag can be recognized at any time.
To ensure that the flag is not sent accidentally, SDLC pro-
cedures require a binary “0” to be inserted by the transmit-
ter after the transmission of any five contiguous “1s”. The
receiver then removes the “0” following a received succes-
sion of five “1s”. Inserted and removed “0s” are not includ-
ed in the CRC calculation.
Beginning Flag
01111110
8 Bits
Address
Figure 4-11. SDLC Message Format
8 Bits
Control
8 Bits
Frame
Any Number
Information
This is accomplished by setting the Loop Mode bit (D1) in
WR10 and then enabling the transmitter by setting bit D3
to WR5 to “1”. At this point the processor should set the Go
Active on Poll bit (D4) in WR10. The final step is to force
the receiver to search for sync characters. If the receiver is
currently disabled the receiver will enter Hunt mode when
it is enabled by setting bit D0 of WR3 to “1”. If the receiver
is already enabled it may be placed in Hunt mode by set-
ting bit D4 of WR3 to “1”. Once the receiver leaves Hunt
mode the transmitter is activated on the following charac-
ter boundary.
“primary station”. The other station is a “secondary sta-
tion”. Not all information transfers need to be initiated by a
primary station. In SDLC mode, a secondary station can
be the initiator.
The basic format for SDLC is a “frame” (Figure 4-11). The
information field is not restricted in format or content and
can be of any reasonable length (including zero). Its
maximum length is that which can be expected to arrive at
the receiver error-free most of the time. Hence, the
determination of maximum length is a function of
communication channel error rate.
There are two unique bit patterns in SDLC mode besides
the flag sequence. They are the Abort and EOP (End of
Poll) sequence. An Abort is a sequence of from seven to
thirteen consecutive “1s” and is used to signal the prema-
ture termination of a frame. The EOP is the bit pattern
“11111110”, which is used in loop applications as a signal
to a secondary station that it may begin transmission.
The address field can consist of one or more octets and is
used to designate the number of secondary station to
which the commands or data are sent. A control field may
follow the address. The control field is eight bits long and
is used to initiate SDLC activities. Data follows the control
field any may consist of any number of bits.
In the SDLC mode, the ISCC operates in the following
way. In SDLC mode, frames of information are opened and
closed by a flag. The Flag character has the unique bit pat-
tern of “01111110”. When transmitting data or CRC, the
Of Bits
16 Bits
Frame
Check
Ending Flag
Z16C35ISCC™ User’s Manual
01111110
Data Communication Modes
8 Bits
4-17
4