Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 102

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Application Note
Interfacing Z80
Worst Case
6.
1.
2.
4.
8.
3.
7.
Worst Case
5.
Z8500
Parameter
TsA(RD)
TdA(DR)
TdRDf(DR)
TwRD1
TsA(WR)
TsDW(WR)
TwWR1
.
Z80A
Parameter
TsD(Cf)
6-6
INPUT/OUTPUT CYCLES (Continued)
TsA(WR)
TsA(RD)
TdA(DR)
TsCEI(WR)
TsCEI(RD)
TwRDI
TwWRI
TdRDf(DR)
TsDW(WR)
TcC
TwCh
TfC
TdCr(A)
TdCr(RDf)
TdCr(IORQf)
TdCr(WRf)
TsD(Cf)
®
CPUs to the Z8500 Peripheral Family
Z80A
Equation
TcC-TdCr(A)
3TcC+TwCh-TdCr(A)-TsD(Cf)
2TcC+TwCh-TsD(Cf)
2TcC+TwCh+TfC-TdCr(RDf)
TcC-TdCr (A)
2TcC+TwCh+TfC-TdCr(WRf)
Z8500
Equation
3TcC+TwCh-TdCr(A)-TdA(DR)
/RD
2TcC+TwCh-TdCr(RDf)-TdRD(DR)
Clock Cycle Period
Clock Cycle High Width
Clock Cycle Fall Time
Clock High to Address Valid
Clock High to /RD Low
Clock High to /IORQ Low
Clock High to /WR Low
Data to Clock Low Setup
Address to /WR to Low Setup
Address to /RD Low Setup
Address to Read Data Valid
/CE Low to /WR Low Setup
/CE Low to /RD Low Setup
/RD Low Width
/WR Low Width
/RD Low to Read Data Valid
Write Data to /WR Low Setup
Table 2. Z8500 Timing Parameters I/O Cycles
Table 3. Z80A Timing Parameters I/O Cycles
Table 5. Parameter Equations
Table 4. Parameter Equations
Min
250
110
50
Min
80
80
390
390
0
Value
140 min
800 min
460 min
525 min
140 min
>0 min
560 min
Value
160 min
135 min
Max
30
110
85
75
65
Max
590
ns
ns
255
Units
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
UM011001-0601