Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 218

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Application Note
Boost Your System Performance Using The Zilog ESCC
RECEIVE FIFO INTERRUPT
In the ESCC, receive interrupt frequencies are reduced
due to a deeper Receive FIFO and the revised receive
interrupt structure.
If WR7' D3 Receive FIFO Interrupt Level bit is reset, the
ESCC generates the receive character available interrupt
on every received character. This is compatible with SCC
Receive Character Available Interrupt. If WR7' D3 is set,
the Receive Character Available Interrupt is triggered
13-6
Figure 5. Flowchart of Receive Interrupt Service Routine to Reduce Receive Interrupt Frequencies
RX FIFO Have
Been Read
All Data in
RX FIFO
Empty
NO
™
From RX FIFO
Level Enabled
RCA Interrupt
when the Receive FIFO is half full; the first four locations
from the entry are still empty. By enabling the receive FIFO
interrupt level, together with polling the Receive Character
Available (RCA) bit in RR0, the receive interrupt
frequencies are reduced significantly. Receive data is read
in blocks of four bytes (Figure 5). This would help to offload
systems which have a long interrupt latency and heavily
loaded Operating Systems.
RX FIFO Int.
Read Data
RCA = '1'?
Service
RR0
YES
UM011001-0601