Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 11

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
2.1 INTRODUCTION
This chapter details the interfacing of the 16C35 ISCC to a
system. Covered in this chapter is a description of the Bus
Interface Unit (BIU) and information about the ISCC in non-
multiplexed and multiplexed bus operation. The following
2.2 BUS INTERFACE UNIT (BIU) DESCRIPTION
The ISCC
patible with a variety of microprocessors and microcontrol-
lers. The device is designed to work with 8- or 16-bit bus
systems and may be used with address/data multiplexed
buses or non-multiplexed buses. The bus interface style is
selected by certain actions which take place after a hard-
ware reset.
The ISCC contains a Bus Configuration Register, the BCR.
This register has no address and is only accessible in the
first transaction to the ISCC after a hardware reset; this first
transaction must be a write with AØ/sec//DMA Low and is
automatically directed to the Bus Configuration Register by
the ISCC. The Bus Configuration Register contains bits
which program the byte swapping feature, the interrupt ac-
knowledge type and other aspects of the bus interface con-
figuration. Refer to Chapter 5 for BCR details.
The multiplexed bus is selected for the ISCC if there is an
Address Strobe prior to or during the transaction which
writes the BCR. If no Address Strobe is present prior to or
during the transaction which writes the BCR, a non-multi-
plexed bus is selected. The address strobe is recognized
whether or not the ISCC Chip Enable is active.
2.2.1 Non-Multiplexed Bus Operation
When the ISCC is initialized for non-multiplexed opera-
tion, register addressing for the ISCC cell is (with the ex-
ception of WR0 and RR0), accomplished using an inter-
nal pointer accessed via WR0. Accessing internal
registers by this means is a two step operation requiring
a write to the pointer followed by access of the desired
register. This is described in detail in later sections. Note
™
contains a flexible bus interface that is com-
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section entails the ISCC’s capabilities for three types of I/O
operations: polling, interrupt (vectored or non-vectored),
and DMA Transfer modes. Also included in this chapter is
information about the ISCC registers and register access.
that when the DMA is not used to address the data, the
data registers must be accessed by pointing to Register 8.
(This is in contrast to the Z8530 which allows direct ad-
dressing of the data registers through the C/D pin.)
When the ISCC is initialized for non-multiplexed operation,
register addressing for the DMA cell (with the exception of
CSAR) is accomplished in a manner similar to that used in
the SCC cell. In this case the pointer is accessed in the
Command Status Address Register (CSAR bits 4 - 0). The
SCC cell and DMA cell pointers are independent. Detailed
operation is described in a later section.
2.2.2 Multiplexed Bus Operation
When the ISCC is initialized for multiplexed bus operation,
all registers in the SCC cell are directly addressable with
the register address occupying AD5 through AD1, or AD4
through AD0 (Shift Left/Shift Right modes). The A0/SCC
//DMA pin controls the SCC cell /DMA selection. The SCC
cell channel A/B selection may be controlled either by the
A0/A//B pin or by the A/B selection in the address on AD7-
AD0 that is strobed into the ISCC with /AS. Use of this re-
quires that the unused SCC channel select option to be set
to Channel A. That is, if the A0/A//B pin is used to select
the channel, then the AD bit for channel selection must se-
lect channel A (the actual bit is determined by the Shift
Left/Shift Right mode employed) and conversely, if the AD
bus bit is used to select the channel, then the A0/A//B pin
must select channel A. Refer to the A0/SCC//DMA and
A1/A//B pin descriptions for the encoding of these signals.
In the multiplexed bus mode of operation, the register
pointer in WR0 of the SCC cell is ignored and has no effect
NTERFACING THE
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ISCC™
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