Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 75

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
Bit 4 is the Go Active On Poll control bit
When Loop mode is first selected during SDLC operation,
the ISCC connects RxD to TxD with only gate delays in the
path. The ISCC does not go on-loop and insert the 1-bit
delay between RxD and TxD until this bit has been set and
an EOP received. When the ISCC is on-loop, the transmit-
ter can not go active unless this bit is set at the time an
EOP is received. The ISCC examines this bit whenever the
transmitter is active in SDLC Loop mode and is sending a
flag. If this bit is set at the time the flag is leaving the Trans-
mit Shift register, another flag or data byte (if the transmit
buffer is full) is transmitted. If the Go Active on Poll bit is
not set at this time, the transmitter finishes sending the flag
and reverts to the 1-Bit Delay mode. Thus, to transmit only
one response frame, this bit should be reset after the first
data byte is sent to the ISCC, but before CRC has been
transmitted. If the bit is not reset before CRC is transmit-
ted, extra flags are sent, slowing down response time on
the loop. If this bit is reset before the first data is written,
the ISCC completes the transmission of the present flag
and reverts to the 1-Bit Delay mode. After gaining control
of the loop, the ISCC is not able to transmit again until a
flag and another EOP have been received. Though not
strictly necessary, it is good practice to set this bit only
upon receipt of a poll frame to ensure that the ISCC does
not go on-loop without the CPU noticing it.
In synchronous modes other than SDLC with the Loop
Mode bit set, this bit must be set before the transmitter can
go active in response to a received sync character.
Manchester
Bit 6
0
0
1
1
Figure 5-12. NRZ (NRZI), FM1 (FM0) Timing
NRZ1
Data
NRZ
FM1
FM0
Table 5-8. Data Encoding
1
Bit 5
0
1
0
1
1
Encoding
NRZ
NRZI
FM1 (transition = 1)
FM0 (transition = 0)
0
0
1
P R E L I M I N A R Y
0
This bit is always ignored in Asynchronous mode and Syn-
chronous modes unless the Loop Mode bit is set. This bit
is reset by a channel or hardware reset.
Bit 3 is the Mark//Flag Idle line control bit
This bit affects only SDLC operation and is used to control
the idle line condition. If this bit is set to “0,” the transmitter
send flags as an idle line. If this bit is set to “1,” the trans-
mitter sends continuous “1s” after the closing flag of a
frame. The idle line condition is selected byte by byte; i.e.,
either a flag or eight “1s” are transmitted. The primary sta-
tion in an SDLC loop should be programmed for Mark Idle
to create the EOP sequence. Mark Idle must be deselect-
ed at the beginning of a frame before the first data is writ-
ten to the ISCC, so that an opening flag can be transmit-
ted. This bit is ignored in Loop mode, but the programmed
value takes effect upon exiting the Loop mode. This bit is
reset by a channel or hardware reset.
Bit 2 is the Abort//Flag On Underrun select bit
This bit affects only SDLC operation and is used to control
how the ISCC responds to a transmit underrun condition.
If this bit is set to “1” and a transmit underrun occurs, the
ISCC sends an abort and a flag instead of CRC. If this bit
is reset, the ISCC sends CRC on a transmit underrun. At
the beginning of this 16-bit transmission, the Transmit Un-
derrun/EOM bit is set, causing an External/Status inter-
rupt. The CPU uses this status, along with the byte count
from memory or the DMA, to determine whether the frame
must be retransmitted. A transmit buffer Empty interrupt
occurs at the end of this 16-bit transmission to start the
next frame. If both this bit and the Mark/Flag Idle bit are set
to “1,” all “1s” are transmitted after the transmit underrun.
This bit should be set after the first byte of data is sent to
the ISCC and reset immediately after the last byte of data
so that the frame will be terminated properly with CRC and
a flag. This bit is ignored in Loop mode, but the pro-
grammed value is active upon exiting Loop mode. This bit
is reset by a channel or hardware reset.
Bit 1 is the Loop Mode control bit
In SDLC mode, the initial set condition of this bit forces the
ISCC to connect TxD to RxD and to begin searching the in-
coming data stream so that it can go on loop. All bits perti-
nent to SDLC mode operation in other registers must be
set before this mode is selected. The transmitter and re-
ceiver should not be enabled until after this mode has been
selected. As soon as the Go Active On Poll bit is set and
an EOP is received, the ISCC goes on-loop. If this bit is re-
set after the ISCC goes on-loop, the ISCC waits for the
next EOP to go off-loop.
Z16C35ISCC™ User’s Manual
Register Descriptions
5-15
5