Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 12

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35 ISCC™ User’s Manual
Interfacing the ISCC™
2.2 BUS INTERFACE UNIT (BIU) DESCRIPTION (Continued)
on the accessing of the internal registers. Register access
is made solely through the latched address. However, the
pointer in the DMA Channel Command/Address Register
functions in the multiplexed bus mode and may be used to
access DMA registers in a manner identical to that in the
non-multiplexed bus mode. To use the DMA pointer in the
multiplexed bus mode, the multiplexed address must al-
ways address the CCAR of the DMA even though the ac-
tual register access will be made according to the pointer.
This requires that in the normal multiplexed mode of oper-
ation with register access through the latched address,
writes to the DMA CCAR must always write zeros to the
pointer field.
In the multiplexed bus mode in some host configurations,
address A0 may be used for byte transfer control in 16-bit
systems. Therefore, it may be necessary to ignore A0 in
the register decode. This is accommodated in the ISCC by
providing an option to decode the multiplexed address
from A1 upwards rather than from A0 upwards. This option
is the Shift Left/Shift Right mode. The Shift Left/Shift Right
modes for the address decoding for the internal registers
(multiplexed bus) are separately programmable for the
SCC cell and for the DMA cell. For the SCC cell the pro-
gramming and operation is identical to that in the SCC;
programming is accomplished through Write Register 0
(WR0), bits 1 and 0 (Figure 5-2). The programming of the
Shift Left/Shift Right modes for the DMA cell is accom-
plished in the BCR, bit 0. In this case, the shift function is
similar to that for the SCC cell; with Shift left, the internal
register addresses are decoded from bits AD5 through
AD1 and with Shift Right, the internal register addresses
are decoded from bits AD4 through AD0.
When the multiplexed bus mode is selected, Write Reg-
ister 0 (WR0) takes on the form of WR0 in the Z8030
(Figure 5-2).
2.2.3 Data Transfers
All data transfers to and from the ISCC are done in bytes
even though the data may at special times occupy the low-
er or upper byte of the 16-bit bus. Bus transfers as a slave
peripheral are done differently than bus transfers when the
ISCC is the bus master during DMA transactions. The
ISCC is fundamentally an 8-bit peripheral but supports 16-
bit buses in the DMA mode. Slave peripheral and DMA
transactions are described in the next paragraphs.
2-2
Data Bus Transfers as a Slave Peripheral: When ac-
cessed as a peripheral device (when the ISCC is not a bus
master performing DMA transfers), only 8 bits are trans-
ferred. When the ISCC registers are read, the byte data
present on the lower 8 bits of the bus is replicated on the
upper 8 bits of the bus. Data is accepted by the ISCC only
on the lower 8 bits of the bus.
ISCC DMA Bus Transfers: During DMA transfers, when
the ISCC is bus master, only byte data is transferred. How-
ever, data may be transferred from the ISCC on the upper
8 bits of the bus or on the lower 8 bits of the bus. Moreover,
odd or even byte transfers may be done on the lower or up-
per 8 bits of the bus. This is programmable and is de-
scribed below.
During DMA transfers to memory from the ISCC, byte data
only is transferred and the data appears on the lower 8 bits
and is replicated on the upper 8 bits of the bus. Thus the
data may be written to an odd or even byte of the system
memory by address decoding and strobe generation.
During DMA transfers to the ISCC from memory, byte data
only is transferred and normally data is accepted only on
the lower 8 bits of the bus. However, the byte swapping
feature may be used to enable data to be accepted on
either the lower or upper 8 bits of the bus. The byte
swapping feature is enabled by programming the Byte
Swap Enable bit to a 1 in the BCR. The odd/even byte
transfer selection is made by programming the Byte Swap
Select bit in the BCR. If Byte Swap Select is a 1, then even
address bytes (transfers where the DMA address has A0
equal 0) are accepted on the lower 8 bits of the bus and
odd address bytes (transfers where the DMA address has
A0 equal 1) are accepted on the upper 8 bits of the bus. If
Byte Swap Select is a 0, then even address bytes
(transfers where the DMA address has A0 equal 0) are
accepted on the upper 8 bits of the bus and odd address
bytes (transfers where the DMA address has A0 equal 1)
are accepted on the lower 8 bits of the bus.
UM011001-0601