Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 70

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35ISCC™ User’s Manual
Register Descriptions
5.4 WRITE REGISTERS (Continued)
Bit combination 01 selects the 16X Mode. The clock rate is
16 times the data rate. In External Sync mode, this bit com-
bination specifies that only the /SYNC pin can be used to
achieve character synchronization.
Bit combination 10 selects the 32X Mode. The clock rate is
32 times the data rate. In External Sync mode, this bit com-
bination specifies that either the /SYNC pin or a match with
the character stored in WR7 will signal character synchro-
nization. The sync character can be either six or eight bits
long as specified by the 6-bit/8-bit Sync bit in WR10.
Bit combination 11 selects the 64X Mode. The clock rate is
64 times the data rate. With this bit combination in External
Sync mode, both the receiver and transmitter are placed in
SDLC mode. The only variation from normal SDLC opera-
tion is that the /SYNC pin can be used to start or stop the
reception of a frame by forcing the receiver to act as
though a flag had been received.
Bits 5 and 4 are the SYNC Mode selection Bits 1 And 0
These two bits select the various options for character syn-
chronization. They are ignored unless synchronous modes
are selected in the stop bits field of this register.
Bit combination 00 selects the Monosync mode. In this
mode, the receiver achieves character synchronization by
matching the character stored in WR7 with an identical
character in the received data stream. The transmitter
uses the character stored in WR6 as a time fill. The sync
character can be either six or eight bits, depending on the
state of the 6-bit/8-bit Sync bit in WR10. if the Sync Char-
acter Load Inhibit bit is set, the receiver strips the contents
of WR6 from the data stream if received within character
boundaries.
Bit combination 01 selects the Bisync mode. The concate-
nation of WR7 with WR6 is used for receiver synchroniza-
tion and as a time fill by the transmitter. The sync character
can be 12 or 16 bits in the receiver, depending on the state
of the 6-bit/8-bit Sync bit in WR10. The transmitted charac-
ter is always 16 bits.
Bit combination 10 selects the SDLC Mode. In this mode,
SDLC is selected and requires a Flag (01111110) to be
written to WR7. The receiver address field should be writ-
ten to WR6. The SDLC CRC polynomial must also be se-
lected (WR5) in SDLC mode.
5-10
P R E L I M I N A R Y
Bit combination 11 selects the External Sync Mode. In this
mode, the ISCC expects external logic to signal character
synchronization via the /SYNC pin. If the crystal oscillator
option is selected (in WR11), the internal /SYNC signal is
forced to “0.” In this mode, the transmitter is in Monosync
mode using the contents of WR6 as the time fill with the
sync character length specified by the 6-bit/8-bit Sync bit
in WR10.
Bits 3 and 2 are the Stop Bits selection, Bits 1 and 0
These bits determine the number of stop bits added to
each asynchronous character that is transmitted. The re-
ceiver always checks for one stop bit in Asynchronous
mode. A Special mode specifies that a Synchronous mode
is to be selected. D2 is always set to “1” by a channel or
hardware reset to ensure that the /SYNC pin is in a known
state after a reset.
Bit combination 00 selects Synchronous Modes Enable.
This bit combination selects one of the synchronous
modes specified by bits D4, D5, D6, and D7 of this register
and forces the 1X Clock mode internally.
Bit combination 01 selects 1 Stop Bit/Character. This bit
combination selects Asynchronous mode with one stop bit
per character.
Bit combination 10 selects 1 1/2 Stop Bits/Character.
These bits select Asynchronous mode with 1-1/2 stop bits
per character. This mode can not be used with the 1X
clock mode.
Bit combination 11 selects 2 Stop Bits/Character. These
bits select Asynchronous mode with two stop bits per
transmitted character and check for one received stop bit.
Bit 1 is the Parity Even//Odd select bit
This bit determines whether parity is checked as an even
or odd. A “1” programmed here selects even parity, and a
“0” selects odd parity. This bit is ignored if the Parity enable
bit is not set.
Bit 0 is the Parity Enable
When this bit is set, an additional bit position beyond
those specified in the bits/character control is added to
the transmitted data and is expected in the receive data.
The Received Parity bit is transferred to the CPU as part
of the data unless eight bits per character is selected in
the receiver.
UM011001-0601