Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 78

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35ISCC™ User’s Manual
Register Descriptions
5.4 WRITE REGISTERS (Continued)
5.4.14 Write Register 13 (Upper Byte of Baud
Rate Generator Time Constant)
WR13 contains the upper byte of the time constant for the
baud rate generator. Bit positions for WR13 are shown in
Figure 5-15.
5.4.15 Write Register 14 (Miscellaneous
Control Bits)
WR14 contains some miscellaneous control bits. Bit posi-
tions for WR14 are shown in Figure 5-16.
5-18
Write Register 14
D7
Write Register 13
D7
0
0
0
0
1
1
1
1
D6
D6
0
0
1
1
0
0
1
1
D5 D4 D3 D2 D1 D0
D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
1
Figure 5-15. Write Register 13
Figure 5-16. Write Register 14
Null Command
Enter Search Mode
Reset Missing Clock
Disable DPLL
Set Source = BR Generator
Set Source = /RTxC
Set FM Mode
Set NRZI Mode
BR Generator Enable
BR Generator Source
/DTR/Request Function
Auto Echo
Local Loopback
TC8
TC9
TC10
TC11
TC12
TC13
TC14
TC15
Upper Byte
of Time
Constant
P R E L I M I N A R Y
Bit D7 and D5 are the Digital Phase-Locked Loop Com-
mand Bits
These three bits encode the eight commands for the Digi-
tal Phase-Locked Loop. A channel or hardware reset dis-
ables the DPLL, resets the missing clock latches, sets the
source to the /RTxC pin and selects NRZI mode. The Enter
Search Mode command enables the DPLL after a reset.
Bit combination 000 is the Null Command. This command
has no effect on the DPLL.
Bit combination 001 is the Enter Search Mode Command.
Issuing this command causes the DPLL to enter the
Search mode, where the DPLL searches for a locking
edge in the incoming data stream. The action taken by the
DPLL upon receipt of this command depends on the oper-
ating mode of the DPLL.
In NRZI mode, the output of the DPLL is High while the
DPLL is waiting for an edge in the incoming data stream.
After the Search mode is entered, the first edge the DPLL
sees is assumed to be a valid data edge, and the DPLL be-
gins the clock recovery operation from that point. The
DPLL clock rate must be 32x the data rate in NRZI mode.
Upon leaving the Search mode, the first sampling edge of
the DPLL occurs 16 of these 32x clocks after the first data
edge and the second sampling occurs 48 of these 32x
clocks after the first data edge. Beyond this point, the
DPLL begins normal operation, adjusting the output to re-
main in sync with the incoming data.
In FM mode, the output of the DPLL is Low while the DPLL
is waiting for an edge in the incoming data stream. The first
edge the DPLL detects is assumed to be a valid clock
edge. For this to be the case, the line must contain only
clock edges; i.e., with FM1 encoding, the line must be con-
tinuous “0s.” With FM0 encoding the line must be continu-
ous “1s,” whereas Manchester encoding requires alternat-
ing “1s” and “0s” on the line. The DPLL clock rate must be
16 times the data rate in FM mode. The DPLL output caus-
es the receiver to sample the data stream in the nominal
center of the two halves of the bit cell to decide whether the
data was a “1” or a “0.” After this command is issued, as in
NRZI mode, the DPLL starts sampling immediately after
the first edge is detected. (In FM mode, the DPLL exam-
ines the clock edge of every other bit cell to decide what
correction must be made to remain in sync.) If the DPLL
does not see an edge during the expected window, the one
clock missing bit in RR10 is set. If the DPLL does not see
an edge after two successive attempts, the two clocks
missing bit in RR10 is set and the DPLL automatically en-
ters the Search mode. This command resets both clock
missing latches.
UM011001-0601