Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 254
Z16C3516VSG
Manufacturer Part Number
Z16C3516VSG
Description
IC 16MHZ Z8500 CMOS ISCC 68-PLCC
Manufacturer
Zilog
Series
IUSC™r
Specifications of Z16C3516VSG
Controller Type
Serial Communications Controller (SCC)
Interface
USB
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
50mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4690-5
Z16C3516VSG
Z16C3516VSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16C3516VSG
Manufacturer:
INTEL
Quantity:
6 219
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Application Note
On-Chip Oscillator Design
Output Level. The signal at the amplifier output should
swing from ground to V
gain in the amplifier. As the oscillator starts up, the signal
amplitude grows until clipping occurs, at which point, the
15-8
PRACTICE: CIRCUIT ELEMENT AND LAY OUT CONSIDERATIONS (Continued)
Must Be Avoided)
(Parallel Traces
Signal C
C L
C
L
CC
Signals A B
EXTAL
. This indicates there is adequate
XTAL
Clock Generator Circuit
2
3
2
3
Z80180
Figure 9. Circuit Board Design Rules
Z80180
64
64
loop gain is effectively reduced to unity and constant
oscillation is achieved. A signal of less than 2.5 Vp-p is an
indication that low gain may be a problem. Either C1/C2
should be made smaller or a low R crystal should be used.
To prevent induced noice, the crystal and load
capacitors should be physically located as
close to the LSI as possible.
Signal lines should not run parallel to the clock
oscillator inputs. In particullar, the clock input
circuitry and the system clock output (pin 64)
should be separated as much as possible.
V
clock oscillator input circuitry.
Resistivity between XTAL or EXTAL and the
other pin should be greater than 10 M
cc
power lines should be separated from the
Board Design Example
1
2
3
(Top View)
20 mm
Z80180
max
GND
64
Layout Should
Lighted Areas
Signal Line
Avoid High
20 mm max
CLK
UM011001-0601
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