Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 217

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
TRANSMIT FIFO INTERRUPT
In the ESCC, transmit interrupt frequencies are reduced by
a deeper Transmit FIFO and the revised transmit interrupt
structure. If the WR7' D5 Transmit FIFO Interrupt Level bit
is reset, the transmit interrupt is generated when the entry
location of the FIFO is empty, i.e., more data can be
written. This is downward compatible with a SCC Transmit
Interrupt since the SCC only has a one-byte transmit buffer
instead of a four-byte Transmit FIFO.
Figure 4. Flowchart of Transmit Interrupt Service Routine to Reduce Transmit Interrupt Frequencies
Transmit FIFO
Transmit FIFO
With Data
Is Loaded
Full
NO
Boost Your System Performance Using The Zilog ESCC
TBE Interrupt
Transmit FIFO
Write Data To
Level Enabled
If WR7' D5 is set, the transmit buffer empty interrupt is
generated when the transmit FIFO is completely empty.
Enabling the transmit FIFO interrupt level, together with
polling the Transmit Buffer Empty (TBE) bit in RR0, causes
significant transmit interrupt frequency reduction. Transmit
data is sent in blocks of four bytes (algorithm is illustrated
in Figure 4). This helps to offload those systems which
have long interrupt latency or a fully loaded Operating
System.
TX FIFO Int.
TBE = '1'?
Service
RR0
YES
Application Note
13-5
™
1