Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 113

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
Z8500/Z8500A Peripherals
Figure 11 depicts logic that can be used in interfacing the
Z80H CPU to the Z8500/Z8500A peripherals. This logic is
the same as that shown in Figure 5, except that a
synchronizing flip-flop is used to recognize an Interrupt
Acknowledge cycle. Since Z8500 peripherals do not rely
upon PCLK except during Interrupt Acknowledge cycles,
synchronization need occur only at that time. Since the
CPU and the peripherals are running at different speeds,
/INTACK and /RD must be synchronized to the Z8500
peripherals clock.
During I/O and normal memory access cycles, the
synchronizing flip-flop and the Shift register remain
cleared because the /M1 signal is inactive. During opcode
fetch cycles, the flip-flop and the Shift register again
remain cleared, but this time because the /MREQ signal is
active. The synchronizing flip-flop allows an Interrupt
Acknowledge cycle to be recognized on the rising edge of
T2 when /M1 is active and /MREQ is inactive, generating
the INTA signal. When INTA is active, the Shift register can
clock and generate /INTACK to the peripheral and /WAIT
to the CPU. The Shift register delays the generation of
/READ to the peripheral until the daisy chain settles. The
Figure 10. Z80A/Z80B CPU to Z8500/Z8500A Peripheral Interrupt Acknowledge Interface Timing
/WAIT signal is removed when sufficient time has been
allowed for the interrupt vector data to be valid.
Figure 12 illustrates Interrupt Acknowledge cycle timing for
the Z80H CPU to Z8500 peripheral interface. Figure 13
illustrates Interrupt Acknowledge cycle timing for the Z80H
CPU to Z8500A peripheral interface. These timing result
from the logic in Figure 11. Should more Wait states be
required, the needed time should be calculated in terms of
PCLKs, not CPU clocks.
Z80 CPU to Z80 and Z8500 Peripherals
In a Z80 system, a combination of Z80 peripherals and
Z8500 peripherals can be used compatibly. While there is
no restriction on the placement of the Z8500 peripherals in
the daisy chain, it is recommended that they be placed
early in the chain to minimize propagation delays during
RET1 cycles.
During an Interrupt Acknowledge cycle, the IEO line from
Z8500 peripherals changes to reflect the interrupt status.
Time should be allowed for this change to ripple through
the remainder of the daisy chain before activating /IORQ
to the Z80 peripherals, or /READ to the Z8500 peripherals.
Interfacing Z80
®
CPUs to the Z8500 Peripheral Family
Application Note
6-17
6