Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 14

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35 ISCC™ User’s Manual
Interfacing the ISCC™
2.3 I/O INTERFACE CAPABILITIES (Continued)
subsequent peripherals. Internally, the SCC cell is higher
priority than the DMA cell. An IUS bit is set during an Inter-
rupt Acknowledge cycle if there are no higher priority de-
vices requesting interrupts. The IUS bit must be cleared by
the CPU. This is usually done at the end of the correspond-
ing interrupt service routine.
Within the SCC portion of the ISCC there are three types
of interrupts: Transmit, Receive, and External/Status.
Each interrupt type is enabled under program control with
Channel A having higher priority than Channel B, and with
Receive, Transmit, and External/Status interrupts priori-
tized in that order within each channel. When the Transmit
interrupt is enabled, the CPU is interrupted when the trans-
mit buffer becomes empty. This implies that data has shift-
ed from the transmit buffer to the transmitter, thus empty-
ing the transmit buffer. When enabled, the receiver
interrupts the CPU in one of three ways:
1. Interrupt on First Receive Character or Special
2. Interrupt on All Receive Characters or Special Receive
3. Interrupt on Special Condition Only
Interrupt on First Character or Special Condition, and In-
terrupt on Special Condition Only, are typically used when
doing block transfers with the DMA. A Special Receive
Condition is one of the following: receiver overrun, framing
error in Asynchronous mode, end-of-frame in SDLC mode
and, optionally, a parity error. The Special Receive Condi-
tion interrupt is different from an Ordinary Receive Charac-
ter Available interrupt only by the status placed in the vec-
tor during the Interrupt Acknowledge cycle. In Interrupt on
First Receive Character, an interrupt occurs from Special
Receive Conditions any time after the First Receive Char-
acter interrupt.
The main function of the External/Status interrupt is to
monitor the signal transitions of the /CTS, /DCD, and
/SYNC pins; however, an External/Status interrupt is also
2-4
Receive Condition
Condition
caused by a Transmit Underrun condition, or a zero count
in the baud rate generator, or by the detection of a Break
(Asynchronous mode), Abort (SDLC mode) or EOP (SDLC
Loop mode) sequence in the data stream. The interrupt
caused by the Abort or EOP has a special feature allowing
the ISCC to interrupt when the Abort or EOP sequence is
detected or terminated. This feature facilitates the proper
termination of the current message, correct initialization of
the next message, and the accurate timing of the Abort
condition in external logic.
2.3.3 DMA Interrupts
Each DMA in the ISCC has two sources of interrupt, which
share an IP bit and an IUS bit, but have independent en-
ables: Terminal Count and Abort. The Abort interrupt is
generated when an active DMA channel is forced to termi-
nate its transfers because /BUSACK is de-asserted during
a transfer. The Terminal Count interrupt is generated when
the DMA transfer count reaches zero. The DMA channels
themselves are prioritized in a fixed order: Receive A,
Transmit A, Receive B, and Transmit B.
When DMA transfers are used, the on-chip DMA channels
transfer data directly to the transmit buffers or directly from
the receive buffers. No other transfers are possible (for ini-
tialization, for example). The request signals from the re-
ceivers and transmitters are hard-wired to the request in-
puts of the DMA channels internally. Each DMA channel
provides a 32-bit address which is either incremented or
decremented with a 16-bit transfer length. Whenever a
DMA channel receives a request from its associated re-
ceiver or transmitter and the DMA channel is enabled, the
ISCC activates the /BUSREQ signal. Upon receipt of an
active /BUSACK, the DMA channel transfers data between
memory and the SCC cell. This transfer continues until the
receiver or transmitter stops requesting a transfer or until
the terminal count is reached, or /BUSACK is deactivated.
The four DMA channels operate independently when the
Request Per Channel option is selected; otherwise, all re-
quests pending at the time of bus acquisition will be ser-
viced before the bus is released. Each DMA channel is in-
dependently enabled and disabled.
UM011001-0601