Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 40

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35ISCC™ User’s Manual
Data Communication Modes
4.2 ASYNCHRONOUS MODE (Continued)
The /CTS pin is ordinarily a simple input to the CTS bit in
RR0. However, if Auto Enables mode is selected this pin
becomes an enable for the transmitter. That is, if Auto En-
ables is on and the /CTS pin is High, the transmitter is dis-
abled; the transmitter is enabled while the /CTS pin is Low.
The transmitter may be programmed to send a Break by
setting bit D4 of WR5 to “1”. The transmitter will send con-
tinuous “0s” from the first transmit clock edge after this
command is issued, until the first transmit clock edge after
this bit is reset. The transmit clock edges referred to here
are those that define transmitted bit cell boundaries.
An additional status bit for use in Asynchronous mode is
available in bit D0 or RR1. This bit, called All Sent, is set
when the transmitter is completely empty and any previous
data or stop bits have reached the TxD pin. The All Sent
bit can be used by the processor as an indication that the
transmitter may be safely disabled.
The initialization sequence for the transmitter in asynchro-
nous mode is given in Table 4-3.
At this point other registers should be initialized according
to the hardware design such as clocking, I/O mode, etc.
When all this is completed, the transmitter may be enabled
by setting WR5(3) = 1. Also note that the transmitter and
receiver may be initialized at the same time.
The number of bits/char is selected by WR3, bits 6-7.
Note: * Initializes transmitter and receiver simultaneously
4.2.2 Asynchronous Reception
During reception, the start and stop bits are stripped away
and checked for errors, leaving only the working data for
CPU interaction.
The receiver always checks for one stop bit. If after char-
acter assembly the receiver finds this stop bit to be a “0”,
the Framing Error bit in the receive error FIFO is set at the
same time that the character is transferred to the receive
4-6
Table 4-3. Initialization Sequence for the Transmitter
WR4
WR3
WR5
Reg
Bit No
3, 2
0, 1
6, 7
6, 5
5
1
4
in Asynchronous Mode
Description
Select Async Mode and the number
of stop bits*
Select parity*
Select clock mode*
Select Auto Enable Mode*
Select modem control (RTS)
Select break generation
Select number of bits/char for
transmitter
data FIFO. This error bit accompanies the data to the top
of the FIFO, where it generates a special receive condition.
The Framing Error bit is not latched, and so must be read
in RR1 before the accompanying data is read.
The additional parity bit per character is transferred to the
receive data FIFO along with the data if the data plus parity
is eight bits or less. The Parity Error bit in the receive error
FIFO may be programmed to cause a special receive con-
dition interrupt by setting bit D2 of WR1 to “1”. This error
bit is latched and so will remain active, once set, until an
Error Reset command has been issued. If interrupts are
not used to transfer data, the Parity Error, Framing Error,
and Overrun Error bits in RR1 should be checked before
the data is removed from the receive data FIFO.
The ISCC™ may be programmed to accept a receive clock
that is one, sixteen, thirty-two, or sixty-four times the data
rate. This is selected by bits D7 and D6 in WR4. The 1X
mode is used when bits are synchronized external to the
receiver. The 1X mode is the only mode in which a data
encoding method other than NRZ may be used. The clock
factor is common to the receiver and transmitter.
The ISCC provides up to three modem control signals as-
sociated with the receiver.
The /SYNC pin is a general-purpose input whose state is
reported in the Sync/Hunt bit in RR0. If the crystal oscillator
is enabled, this pin is not available and the Sync/Hunt bit
is forced to “0”. Otherwise, the /SYNC pin may be used to
carry the Ring Indicator signal.
The /DTR//REQ pin carries the inverted state of the DTR
bit (D7) in WR5 unless this pin has been programmed to
carry a DMA Request signal.
The /DCD pin is ordinarily a simple input to the DCD bit in
RR0. However, if the Auto Enables mode is selected by
setting D5 of WR3 to “1”, this pin becomes an enable for
the receiver. That is, if Auto Enables is on and the /DCD
pin is High, the receiver is disabled. While the /DCD pin is
Low, the receiver is enabled.
The break condition is continuous “0s”, as opposed to the
usual continuous ones during an idle. The ISCC recog-
nizes the Break condition upon seeing a null character
(all “0s”) plus a framing error. Upon recognizing this se-
quence the Break bit in RR0 will be set and will remain set
until a “1” is received. At this point the break condition is
no longer present. At the termination of a break the re-
ceive data FIFO contains a single null character, which
should be read and discarded. The Framing Error bit will
not be set for this character, but if odd parity has been se-
lected, the Parity Error bit will be set. Caution should be
exercised if the receive data line contains a switch that is
UM011001-0601